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Sat, 15 Feb 2020 11:17:28 +0100 (CET) X-Virus-Scanned: amavisd-new at c-s.fr Received: from messagerie.si.c-s.fr ([127.0.0.1]) by localhost (messagerie.si.c-s.fr [127.0.0.1]) (amavisd-new, port 10023) with ESMTP id cXg6Z6Js6SoI; Sat, 15 Feb 2020 11:17:28 +0100 (CET) Received: from [192.168.4.90] (unknown [192.168.4.90]) by messagerie.si.c-s.fr (Postfix) with ESMTP id E2B928B755; Sat, 15 Feb 2020 11:17:27 +0100 (CET) Subject: Re: [PATCH] powerpc/8xx: Fix clearing of bits 20-23 in ITLB miss To: Leonardo Bras , Benjamin Herrenschmidt , Paul Mackerras , Michael Ellerman References: <4f70c2778163affce8508a210f65d140e84524b4.1581272050.git.christophe.leroy@c-s.fr> <546ce4737f308a4ba99a53f550de5b44abc06444.camel@linux.ibm.com> From: Christophe Leroy Message-ID: <1d6a53ab-ea72-7452-ea5f-43dd70b223c9@c-s.fr> Date: Sat, 15 Feb 2020 11:17:27 +0100 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.5.0 MIME-Version: 1.0 In-Reply-To: <546ce4737f308a4ba99a53f550de5b44abc06444.camel@linux.ibm.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: fr Content-Transfer-Encoding: 8bit X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Le 15/02/2020 à 07:28, Leonardo Bras a écrit : > On Sun, 2020-02-09 at 18:14 +0000, Christophe Leroy wrote: >> In ITLB miss handled the line supposed to clear bits 20-23 on the >> L2 ITLB entry is buggy and does indeed nothing, leading to undefined >> value which could allow execution when it shouldn't. >> >> Properly do the clearing with the relevant instruction. >> >> Fixes: 74fabcadfd43 ("powerpc/8xx: don't use r12/SPRN_SPRG_SCRATCH2 in TLB Miss handlers") >> Cc: stable@vger.kernel.org >> Signed-off-by: Christophe Leroy >> --- >> arch/powerpc/kernel/head_8xx.S | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S >> index 9922306ae512..073a651787df 100644 >> --- a/arch/powerpc/kernel/head_8xx.S >> +++ b/arch/powerpc/kernel/head_8xx.S >> @@ -256,7 +256,7 @@ InstructionTLBMiss: >> * set. All other Linux PTE bits control the behavior >> * of the MMU. >> */ >> - rlwimi r10, r10, 0, 0x0f00 /* Clear bits 20-23 */ >> + rlwinm r10, r10, 0, ~0x0f00 /* Clear bits 20-23 */ >> rlwimi r10, r10, 4, 0x0400 /* Copy _PAGE_EXEC into bit 21 */ >> ori r10, r10, RPN_PATTERN | 0x200 /* Set 22 and 24-27 */ >> mtspr SPRN_MI_RPN, r10 /* Update TLB entry */ > > Looks a valid change. > rlwimi r10, r10, 0, 0x0f00 means: > r10 = ((r10 << 0) & 0x0f00) | (r10 & ~0x0f00) which ends up being > r10 = r10 > > On ISA, rlwinm is recommended for clearing high order bits. > rlwinm r10, r10, 0, ~0x0f00 means: > r10 = (r10 << 0) & ~0x0f00 > > Which does exactly what the comments suggests. > > FWIW: > Reviwed-by: Leonardo Bras > I guess you mean Reviewed-by: Leonardo Bras