From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
To: benh@kernel.crashing.org, paulus@samba.org, mpe@ellerman.id.au
Cc: linuxppc-dev@lists.ozlabs.org,
"Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
Subject: [PATCH v6 4/7] powerpc/mm: Add radix__tlb_flush_pte
Date: Fri, 25 Nov 2016 21:32:54 +0530 [thread overview]
Message-ID: <20161125160257.9158-5-aneesh.kumar@linux.vnet.ibm.com> (raw)
In-Reply-To: <20161125160257.9158-1-aneesh.kumar@linux.vnet.ibm.com>
Now that we have page size details encoded in pte using software pte bits,
use that to find page size needed for tlb flush.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/book3s/64/tlbflush-radix.h | 2 ++
arch/powerpc/mm/tlb-radix.c | 11 +++++++++++
2 files changed, 13 insertions(+)
diff --git a/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h b/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h
index a9e19cb2f7c5..e9bbd10ee7e9 100644
--- a/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h
+++ b/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h
@@ -42,4 +42,6 @@ extern void radix__flush_tlb_lpid_va(unsigned long lpid, unsigned long gpa,
unsigned long page_size);
extern void radix__flush_tlb_lpid(unsigned long lpid);
extern void radix__flush_tlb_all(void);
+extern void radix__flush_tlb_pte(unsigned long old_pte, struct mm_struct *mm,
+ unsigned long address);
#endif
diff --git a/arch/powerpc/mm/tlb-radix.c b/arch/powerpc/mm/tlb-radix.c
index 3493cf4e0452..9a1084b45bb5 100644
--- a/arch/powerpc/mm/tlb-radix.c
+++ b/arch/powerpc/mm/tlb-radix.c
@@ -428,3 +428,14 @@ void radix__flush_tlb_all(void)
: : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(0) : "memory");
asm volatile("eieio; tlbsync; ptesync": : :"memory");
}
+
+void radix__flush_tlb_pte(unsigned long old_pte, struct mm_struct *mm,
+ unsigned long address)
+{
+ if (old_pte & _PAGE_LARGE)
+ radix__flush_tlb_page_psize(mm, address, MMU_PAGE_2M);
+ else if (old_pte & _PAGE_GIGANTIC)
+ radix__flush_tlb_page_psize(mm, address, MMU_PAGE_1G);
+ else
+ radix__flush_tlb_page_psize(mm, address, mmu_virtual_psize);
+}
--
2.10.2
next prev parent reply other threads:[~2016-11-25 16:03 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-11-25 16:02 [PATCH v6 0/7] Radix pte update tlbflush optimizations Aneesh Kumar K.V
2016-11-25 16:02 ` [PATCH v6 1/7] powerpc/mm: Rename hugetlb-radix.h to hugetlb.h Aneesh Kumar K.V
2016-11-25 16:02 ` [PATCH v6 2/7] powerpc/mm/hugetlb: Handle hugepage size supported by hash config Aneesh Kumar K.V
2016-11-25 16:02 ` [PATCH v6 3/7] powerpc/mm: Introduce _PAGE_GIGANTIC and _PAGE_LARGE software pte bits Aneesh Kumar K.V
2016-11-25 16:02 ` Aneesh Kumar K.V [this message]
2016-11-25 16:02 ` [PATCH v6 5/7] powerpc/mm: update radix__ptep_set_access_flag to not do full mm tlb flush Aneesh Kumar K.V
2016-11-25 16:02 ` [PATCH v6 6/7] powerpc/mm: update radix__pte_update " Aneesh Kumar K.V
2016-11-25 16:02 ` [PATCH v6 7/7] powerpc/mm: Batch tlb flush when invalidating pte entries Aneesh Kumar K.V
2016-11-26 13:44 ` [PATCH v6 0/7] Radix pte update tlbflush optimizations Aneesh Kumar K.V
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