From: Alexey Kardashevskiy <aik@ozlabs.ru>
To: linuxppc-dev@lists.ozlabs.org
Cc: "Jose Ricardo Ziviani" <joserz@linux.ibm.com>,
"Alexey Kardashevskiy" <aik@ozlabs.ru>,
"Alistair Popple" <alistair@popple.id.au>,
"Daniel Henrique Barboza" <danielhb413@gmail.com>,
"Alex Williamson" <alex.williamson@redhat.com>,
kvm-ppc@vger.kernel.org, "Sam Bobroff" <sbobroff@linux.ibm.com>,
"Piotr Jaroszynski" <pjaroszynski@nvidia.com>,
"Leonardo Augusto Guimarães Garcia" <lagarcia@br.ibm.com>,
"Reza Arbab" <arbab@linux.ibm.com>,
"David Gibson" <david@gibson.dropbear.id.au>
Subject: [PATCH kernel v5 04/20] powerpc/powernv: Move npu struct from pnv_phb to pci_controller
Date: Thu, 13 Dec 2018 17:17:18 +1100 [thread overview]
Message-ID: <20181213061734.16651-5-aik@ozlabs.ru> (raw)
In-Reply-To: <20181213061734.16651-1-aik@ozlabs.ru>
The powernv PCI code stores NPU data in the pnv_phb struct. The latter
is referenced by pci_controller::private_data. We are going to have NPU2
support in the pseries platform as well but it does not store any
private_data in in the pci_controller struct; and even if it did,
it would be a different data structure.
This makes npu a pointer and stores it one level higher in
the pci_controller struct.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
---
Changes:
v5:
* removed !npu checks as this is out of scope of this patch
* added WARN_ON_ONCE in WARN_ON_ONCE(pnv_npu2_init(phb))
v4:
* changed subj from "powerpc/powernv: Detach npu struct from pnv_phb"
* got rid of global list of npus - store them now in pci_controller
* got rid of npdev_to_npu() helper
---
arch/powerpc/include/asm/pci-bridge.h | 1 +
arch/powerpc/platforms/powernv/pci.h | 16 -----
arch/powerpc/platforms/powernv/npu-dma.c | 74 +++++++++++++++++------
arch/powerpc/platforms/powernv/pci-ioda.c | 2 +-
4 files changed, 58 insertions(+), 35 deletions(-)
diff --git a/arch/powerpc/include/asm/pci-bridge.h b/arch/powerpc/include/asm/pci-bridge.h
index 94d4490..aee4fcc 100644
--- a/arch/powerpc/include/asm/pci-bridge.h
+++ b/arch/powerpc/include/asm/pci-bridge.h
@@ -129,6 +129,7 @@ struct pci_controller {
#endif /* CONFIG_PPC64 */
void *private_data;
+ struct npu *npu;
};
/* These are used for config access before all the PCI probing
diff --git a/arch/powerpc/platforms/powernv/pci.h b/arch/powerpc/platforms/powernv/pci.h
index 2131373..f2d50974 100644
--- a/arch/powerpc/platforms/powernv/pci.h
+++ b/arch/powerpc/platforms/powernv/pci.h
@@ -8,9 +8,6 @@
struct pci_dn;
-/* Maximum possible number of ATSD MMIO registers per NPU */
-#define NV_NMMU_ATSD_REGS 8
-
enum pnv_phb_type {
PNV_PHB_IODA1 = 0,
PNV_PHB_IODA2 = 1,
@@ -176,19 +173,6 @@ struct pnv_phb {
unsigned int diag_data_size;
u8 *diag_data;
- /* Nvlink2 data */
- struct npu {
- int index;
- __be64 *mmio_atsd_regs[NV_NMMU_ATSD_REGS];
- unsigned int mmio_atsd_count;
-
- /* Bitmask for MMIO register usage */
- unsigned long mmio_atsd_usage;
-
- /* Do we need to explicitly flush the nest mmu? */
- bool nmmu_flush;
- } npu;
-
int p2p_target_count;
};
diff --git a/arch/powerpc/platforms/powernv/npu-dma.c b/arch/powerpc/platforms/powernv/npu-dma.c
index 91d488f..5e66439 100644
--- a/arch/powerpc/platforms/powernv/npu-dma.c
+++ b/arch/powerpc/platforms/powernv/npu-dma.c
@@ -327,6 +327,25 @@ struct pnv_ioda_pe *pnv_pci_npu_setup_iommu(struct pnv_ioda_pe *npe)
return gpe;
}
+/*
+ * NPU2 ATS
+ */
+/* Maximum possible number of ATSD MMIO registers per NPU */
+#define NV_NMMU_ATSD_REGS 8
+
+/* An NPU descriptor, valid for POWER9 only */
+struct npu {
+ int index;
+ __be64 *mmio_atsd_regs[NV_NMMU_ATSD_REGS];
+ unsigned int mmio_atsd_count;
+
+ /* Bitmask for MMIO register usage */
+ unsigned long mmio_atsd_usage;
+
+ /* Do we need to explicitly flush the nest mmu? */
+ bool nmmu_flush;
+};
+
/* Maximum number of nvlinks per npu */
#define NV_MAX_LINKS 6
@@ -478,7 +497,6 @@ static void acquire_atsd_reg(struct npu_context *npu_context,
int i, j;
struct npu *npu;
struct pci_dev *npdev;
- struct pnv_phb *nphb;
for (i = 0; i <= max_npu2_index; i++) {
mmio_atsd_reg[i].reg = -1;
@@ -493,8 +511,7 @@ static void acquire_atsd_reg(struct npu_context *npu_context,
if (!npdev)
continue;
- nphb = pci_bus_to_host(npdev->bus)->private_data;
- npu = &nphb->npu;
+ npu = pci_bus_to_host(npdev->bus)->npu;
mmio_atsd_reg[i].npu = npu;
mmio_atsd_reg[i].reg = get_mmio_atsd_reg(npu);
while (mmio_atsd_reg[i].reg < 0) {
@@ -662,6 +679,7 @@ struct npu_context *pnv_npu2_init_context(struct pci_dev *gpdev,
struct pnv_phb *nphb;
struct npu *npu;
struct npu_context *npu_context;
+ struct pci_controller *hose;
/*
* At present we don't support GPUs connected to multiple NPUs and I'm
@@ -689,8 +707,9 @@ struct npu_context *pnv_npu2_init_context(struct pci_dev *gpdev,
return ERR_PTR(-EINVAL);
}
- nphb = pci_bus_to_host(npdev->bus)->private_data;
- npu = &nphb->npu;
+ hose = pci_bus_to_host(npdev->bus);
+ nphb = hose->private_data;
+ npu = hose->npu;
/*
* Setup the NPU context table for a particular GPU. These need to be
@@ -764,7 +783,7 @@ struct npu_context *pnv_npu2_init_context(struct pci_dev *gpdev,
*/
WRITE_ONCE(npu_context->npdev[npu->index][nvlink_index], npdev);
- if (!nphb->npu.nmmu_flush) {
+ if (!npu->nmmu_flush) {
/*
* If we're not explicitly flushing ourselves we need to mark
* the thread for global flushes
@@ -802,6 +821,7 @@ void pnv_npu2_destroy_context(struct npu_context *npu_context,
struct pci_dev *npdev = pnv_pci_get_npu_dev(gpdev, 0);
struct device_node *nvlink_dn;
u32 nvlink_index;
+ struct pci_controller *hose;
if (WARN_ON(!npdev))
return;
@@ -809,8 +829,9 @@ void pnv_npu2_destroy_context(struct npu_context *npu_context,
if (!firmware_has_feature(FW_FEATURE_OPAL))
return;
- nphb = pci_bus_to_host(npdev->bus)->private_data;
- npu = &nphb->npu;
+ hose = pci_bus_to_host(npdev->bus);
+ nphb = hose->private_data;
+ npu = hose->npu;
nvlink_dn = of_parse_phandle(npdev->dev.of_node, "ibm,nvlink", 0);
if (WARN_ON(of_property_read_u32(nvlink_dn, "ibm,npu-link-index",
&nvlink_index)))
@@ -888,9 +909,15 @@ int pnv_npu2_init(struct pnv_phb *phb)
struct pci_dev *gpdev;
static int npu_index;
uint64_t rc = 0;
+ struct pci_controller *hose = phb->hose;
+ struct npu *npu;
+ int ret;
- phb->npu.nmmu_flush =
- of_property_read_bool(phb->hose->dn, "ibm,nmmu-flush");
+ npu = kzalloc(sizeof(*npu), GFP_KERNEL);
+ if (!npu)
+ return -ENOMEM;
+
+ npu->nmmu_flush = of_property_read_bool(hose->dn, "ibm,nmmu-flush");
for_each_child_of_node(phb->hose->dn, dn) {
gpdev = pnv_pci_get_gpu_dev(get_pci_dev(dn));
if (gpdev) {
@@ -904,18 +931,29 @@ int pnv_npu2_init(struct pnv_phb *phb)
}
}
- for (i = 0; !of_property_read_u64_index(phb->hose->dn, "ibm,mmio-atsd",
+ for (i = 0; !of_property_read_u64_index(hose->dn, "ibm,mmio-atsd",
i, &mmio_atsd); i++)
- phb->npu.mmio_atsd_regs[i] = ioremap(mmio_atsd, 32);
+ npu->mmio_atsd_regs[i] = ioremap(mmio_atsd, 32);
- pr_info("NPU%lld: Found %d MMIO ATSD registers", phb->opal_id, i);
- phb->npu.mmio_atsd_count = i;
- phb->npu.mmio_atsd_usage = 0;
+ pr_info("NPU%d: Found %d MMIO ATSD registers", hose->global_number, i);
+ npu->mmio_atsd_count = i;
+ npu->mmio_atsd_usage = 0;
npu_index++;
- if (WARN_ON(npu_index >= NV_MAX_NPUS))
- return -ENOSPC;
+ if (WARN_ON(npu_index >= NV_MAX_NPUS)) {
+ ret = -ENOSPC;
+ goto fail_exit;
+ }
max_npu2_index = npu_index;
- phb->npu.index = npu_index;
+ npu->index = npu_index;
+ hose->npu = npu;
return 0;
+
+fail_exit:
+ for (i = 0; i < npu->mmio_atsd_count; ++i)
+ iounmap(npu->mmio_atsd_regs[i]);
+
+ kfree(npu);
+
+ return ret;
}
diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c
index 29c6837..8528fb9 100644
--- a/arch/powerpc/platforms/powernv/pci-ioda.c
+++ b/arch/powerpc/platforms/powernv/pci-ioda.c
@@ -1283,7 +1283,7 @@ static void pnv_pci_ioda_setup_PEs(void)
pnv_ioda_reserve_pe(phb, 0);
pnv_ioda_setup_npu_PEs(hose->bus);
if (phb->model == PNV_PHB_MODEL_NPU2)
- pnv_npu2_init(phb);
+ WARN_ON_ONCE(pnv_npu2_init(phb));
}
if (phb->type == PNV_PHB_NPU_OCAPI) {
bus = hose->bus;
--
2.17.1
next prev parent reply other threads:[~2018-12-13 6:23 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-13 6:17 [PATCH kernel v5 00/20] powerpc/powernv/npu, vfio: NVIDIA V100 + P9 passthrough Alexey Kardashevskiy
2018-12-13 6:17 ` [PATCH kernel v5 01/20] powerpc/ioda/npu: Call skiboot's hot reset hook when disabling NPU2 Alexey Kardashevskiy
2018-12-13 6:17 ` [PATCH kernel v5 02/20] powerpc/mm/iommu/vfio_spapr_tce: Change mm_iommu_get to reference a region Alexey Kardashevskiy
2018-12-13 6:17 ` [PATCH kernel v5 03/20] powerpc/vfio/iommu/kvm: Do not pin device memory Alexey Kardashevskiy
2018-12-14 3:18 ` Paul Mackerras
2018-12-18 23:33 ` Michael Ellerman
2018-12-13 6:17 ` Alexey Kardashevskiy [this message]
2018-12-13 6:17 ` [PATCH kernel v5 05/20] powerpc/powernv/npu: Move OPAL calls away from context manipulation Alexey Kardashevskiy
2018-12-13 6:17 ` [PATCH kernel v5 06/20] powerpc/pseries/iommu: Use memory@ nodes in max RAM address calculation Alexey Kardashevskiy
2018-12-13 6:17 ` [PATCH kernel v5 07/20] powerpc/pseries/npu: Enable platform support Alexey Kardashevskiy
2018-12-13 6:17 ` [PATCH kernel v5 08/20] powerpc/pseries: Remove IOMMU API support for non-LPAR systems Alexey Kardashevskiy
2018-12-13 6:17 ` [PATCH kernel v5 09/20] powerpc/powernv/pseries: Rework device adding to IOMMU groups Alexey Kardashevskiy
2018-12-13 6:17 ` [PATCH kernel v5 10/20] powerpc/iommu_api: Move IOMMU groups setup to a single place Alexey Kardashevskiy
2018-12-18 23:35 ` Michael Ellerman
2018-12-19 6:17 ` Alexey Kardashevskiy
2018-12-19 9:51 ` Michael Ellerman
2018-12-13 6:17 ` [PATCH kernel v5 11/20] powerpc/powernv: Reference iommu_table while it is linked to a group Alexey Kardashevskiy
2018-12-13 6:17 ` [PATCH kernel v5 12/20] powerpc/powernv/npu: Move single TVE handling to NPU PE Alexey Kardashevskiy
2018-12-13 6:17 ` [PATCH kernel v5 13/20] powerpc/powernv/npu: Convert NPU IOMMU helpers to iommu_table_group_ops Alexey Kardashevskiy
2018-12-13 6:17 ` [PATCH kernel v5 14/20] powerpc/powernv/npu: Add compound IOMMU groups Alexey Kardashevskiy
2018-12-19 0:17 ` Michael Ellerman
2018-12-19 6:54 ` Alexey Kardashevskiy
2018-12-19 10:00 ` Michael Ellerman
2018-12-20 2:18 ` Alexey Kardashevskiy
2018-12-20 5:33 ` Michael Ellerman
2018-12-13 6:17 ` [PATCH kernel v5 15/20] powerpc/powernv/npu: Add release_ownership hook Alexey Kardashevskiy
2018-12-13 6:17 ` [PATCH kernel v5 16/20] powerpc/powernv/npu: Check mmio_atsd array bounds when populating Alexey Kardashevskiy
2018-12-13 6:17 ` [PATCH kernel v5 17/20] powerpc/powernv/npu: Fault user page into the hypervisor's pagetable Alexey Kardashevskiy
2018-12-13 6:17 ` [PATCH kernel v5 18/20] vfio_pci: Allow mapping extra regions Alexey Kardashevskiy
2018-12-13 6:17 ` [PATCH kernel v5 19/20] vfio_pci: Allow regions to add own capabilities Alexey Kardashevskiy
2018-12-13 6:17 ` [PATCH kernel v5 20/20] vfio_pci: Add NVIDIA GV100GL [Tesla V100 SXM2] subdriver Alexey Kardashevskiy
2018-12-18 22:37 ` Alex Williamson
2018-12-19 4:36 ` Alexey Kardashevskiy
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