From: Madhavan Srinivasan <maddy@linux.ibm.com>
To: mpe@ellerman.id.au
Cc: atrajeev@linux.vnet.ibm.com, linuxppc-dev@lists.ozlabs.org,
Madhavan Srinivasan <maddy@linux.ibm.com>
Subject: [PATCH v2 2/5] powerpc/perf: Drop the check for SIAR_VALID
Date: Wed, 21 Oct 2020 14:23:26 +0530 [thread overview]
Message-ID: <20201021085329.384535-2-maddy@linux.ibm.com> (raw)
In-Reply-To: <20201021085329.384535-1-maddy@linux.ibm.com>
From: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
In power10 DD1, there is an issue that causes the SIAR_VALID
bit of Sampled Instruction Event Register(SIER) not to be
set. But the SIAR_VALID bit is used for fetching the instruction
address from Sampled Instruction Address Register(SIAR), and
marked events are sampled only if the SIAR_VALID bit is set.
So drop the check for SIAR_VALID and return true always incase of
power10 DD1.
Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com>
---
Changelog v1:
- Drop the check for SIER[CMPL] and retur true instead
- Made changes to commit message
arch/powerpc/perf/core-book3s.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c
index 08643cba1494..3b62dbb94796 100644
--- a/arch/powerpc/perf/core-book3s.c
+++ b/arch/powerpc/perf/core-book3s.c
@@ -350,7 +350,14 @@ static inline int siar_valid(struct pt_regs *regs)
int marked = mmcra & MMCRA_SAMPLE_ENABLE;
if (marked) {
- if (ppmu->flags & PPMU_HAS_SIER)
+ /*
+ * SIER[SIAR_VALID] is not set for some
+ * marked events on power10 DD1, so drop
+ * the check for SIER[SIAR_VALID] and return true.
+ */
+ if (ppmu->flags & PPMU_P10_DD1)
+ return 0x1;
+ else if (ppmu->flags & PPMU_HAS_SIER)
return regs->dar & SIER_SIAR_VALID;
if (ppmu->flags & PPMU_SIAR_VALID)
--
2.26.2
next prev parent reply other threads:[~2020-10-21 8:57 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-21 8:53 [PATCH 1/5] powerpc/perf: Add new power pmu flag "PPMU_P10_DD1" for power10 DD1 Madhavan Srinivasan
2020-10-21 8:53 ` Madhavan Srinivasan [this message]
2020-10-21 8:53 ` [PATCH 3/5] powerpc/perf: Use the address from SIAR register to set cpumode flags Madhavan Srinivasan
2020-10-21 8:53 ` [PATCH 4/5] powerpc/perf: Exclude kernel samples while counting events in user space Madhavan Srinivasan
2020-10-21 8:53 ` [PATCH 5/5] powerpc/perf: use regs->nip when siar is zero Madhavan Srinivasan
2020-10-21 9:13 ` Christophe Leroy
2020-10-22 1:25 ` Michael Ellerman
2020-10-27 2:31 ` Madhavan Srinivasan
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