From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E8E3AC0650E for ; Mon, 8 Jul 2019 01:56:44 +0000 (UTC) Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A647B2053B for ; Mon, 8 Jul 2019 01:56:44 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A647B2053B Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=ellerman.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 45hpTk6S8XzDqWS for ; Mon, 8 Jul 2019 11:56:42 +1000 (AEST) Received: from ozlabs.org (bilbo.ozlabs.org [IPv6:2401:3900:2:1::2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 45hng315VzzDqQJ for ; Mon, 8 Jul 2019 11:19:43 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=ellerman.id.au Received: by ozlabs.org (Postfix, from userid 1034) id 45hng26v5bz9sP6; Mon, 8 Jul 2019 11:19:42 +1000 (AEST) X-powerpc-patch-notification: thanks X-powerpc-patch-commit: 3fefd1cd95df04da67c83c1cb93b663f04b3324f In-Reply-To: <20190620060040.26945-1-mikey@neuling.org> To: Michael Neuling From: Michael Ellerman Subject: Re: [PATCH] KVM: PPC: Book3S HV: Fix CR0 setting in TM emulation Message-Id: <45hng26v5bz9sP6@ozlabs.org> Date: Mon, 8 Jul 2019 11:19:42 +1000 (AEST) X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mikey@neuling.org, linuxppc-dev@lists.ozlabs.org, kvm-ppc@vger.kernel.org, sjitindarsingh@gmail.com Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On Thu, 2019-06-20 at 06:00:40 UTC, Michael Neuling wrote: > When emulating tsr, treclaim and trechkpt, we incorrectly set CR0. The > code currently sets: > CR0 <- 00 || MSR[TS] > but according to the ISA it should be: > CR0 <- 0 || MSR[TS] || 0 > > This fixes the bit shift to put the bits in the correct location. > > Tested-by: Suraj Jitindar Singh > Signed-off-by: Michael Neuling Applied to powerpc next, thanks. https://git.kernel.org/powerpc/c/3fefd1cd95df04da67c83c1cb93b663f04b3324f cheers