From: "Alastair D'Silva" <alastair@au1.ibm.com>
To: Christophe Leroy <christophe.leroy@c-s.fr>
Cc: linux-kernel@vger.kernel.org, stable@vger.kernel.org,
Paul Mackerras <paulus@samba.org>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Thomas Gleixner <tglx@linutronix.de>,
linuxppc-dev@lists.ozlabs.org
Subject: Re: [PATCH 1/2] powerpc: Allow flush_icache_range to work across ranges >4GB
Date: Mon, 12 Aug 2019 11:19:49 +1000 [thread overview]
Message-ID: <72a3fca157a508a9f1bc6ea20801b9227d788f1d.camel@au1.ibm.com> (raw)
In-Reply-To: <a9bcc457-9f9b-7010-6796-fb263135f8bc@c-s.fr>
On Fri, 2019-08-09 at 10:59 +0200, Christophe Leroy wrote:
>
> Le 09/08/2019 à 02:45, Alastair D'Silva a écrit :
> > From: Alastair D'Silva <alastair@d-silva.org>
> >
> > When calling flush_icache_range with a size >4GB, we were masking
> > off the upper 32 bits, so we would incorrectly flush a range
> > smaller
> > than intended.
> >
> > This patch replaces the 32 bit shifts with 64 bit ones, so that
> > the full size is accounted for.
> >
> > Heads-up for backporters: the old version of flush_dcache_range is
> > subject to a similar bug (this has since been replaced with a C
> > implementation).
>
> Can you submit a patch to stable, explaining this ?
>
This patch was sent to stable too - or did you mean send another patch
for the stable asm version of flush_dcache_range?
--
Alastair D'Silva
Open Source Developer
Linux Technology Centre, IBM Australia
mob: 0423 762 819
next prev parent reply other threads:[~2019-08-12 1:21 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-09 0:45 [PATCH 1/2] powerpc: Allow flush_icache_range to work across ranges >4GB Alastair D'Silva
2019-08-09 8:59 ` Christophe Leroy
2019-08-12 1:19 ` Alastair D'Silva [this message]
2019-08-12 5:41 ` Christophe Leroy
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