From: Guo Ren <ren_guo@c-sky.com>
To: akpm@linux-foundation.org, arnd@arndb.de,
daniel.lezcano@linaro.org, davem@davemloft.net,
gregkh@linuxfoundation.org, jason@lakedaemon.net,
marc.zyngier@arm.com, mark.rutland@arm.com,
mchehab+samsung@kernel.org, peterz@infradead.org,
robh@kernel.org, robh+dt@kernel.org, tglx@linutronix.de
Cc: linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org,
devicetree@vger.kernel.org, green.hu@gmail.com,
palmer@sifive.com, Guo Ren <ren_guo@c-sky.com>
Subject: [PATCH V5 30/30] clocksource: add gx6605s SOC system timer
Date: Tue, 25 Sep 2018 07:39:33 +0800 [thread overview]
Message-ID: <01ec4f18d0857d76312758c13a9c44204d82039e.1537789737.git.ren_guo@c-sky.com> (raw)
In-Reply-To: <a23b652c2ab55b129f729a57ec765550da1d2c16.1537789737.git.ren_guo@c-sky.com>
In-Reply-To: <cover.1537789736.git.ren_guo@c-sky.com>
Changelog:
- Add COMPILE_TEST in Kconfig
- Add License and Copyright
- Use timer-of framework
- Change name with upstream feedback
- Use clksource_mmio framework
Signed-off-by: Guo Ren <ren_guo@c-sky.com>
---
drivers/clocksource/Kconfig | 8 ++
drivers/clocksource/Makefile | 1 +
drivers/clocksource/timer-gx6605s.c | 150 ++++++++++++++++++++++++++++++++++++
3 files changed, 159 insertions(+)
create mode 100644 drivers/clocksource/timer-gx6605s.c
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index a28043f..3dc24ca 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -628,4 +628,12 @@ config CSKY_MPTIMER
Say yes here to enable C-SKY SMP timer driver used for C-SKY SMP
system.
+config GX6605S_TIMER
+ bool "Gx6605s SOC system timer driver" if COMPILE_TEST
+ depends on CSKY
+ select CLKSRC_MMIO
+ select TIMER_OF
+ help
+ This option enables support for gx6605s SOC's timer.
+
endmenu
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 848c676..7a1b0f4 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -80,3 +80,4 @@ obj-$(CONFIG_X86_NUMACHIP) += numachip.o
obj-$(CONFIG_ATCPIT100_TIMER) += timer-atcpit100.o
obj-$(CONFIG_RISCV_TIMER) += riscv_timer.o
obj-$(CONFIG_CSKY_MPTIMER) += csky_mptimer.o
+obj-$(CONFIG_GX6605S_TIMER) += timer-gx6605s.o
diff --git a/drivers/clocksource/timer-gx6605s.c b/drivers/clocksource/timer-gx6605s.c
new file mode 100644
index 0000000..3974ede
--- /dev/null
+++ b/drivers/clocksource/timer-gx6605s.c
@@ -0,0 +1,150 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/sched_clock.h>
+
+#include "timer-of.h"
+
+#define CLKSRC_OFFSET 0x40
+
+#define TIMER_STATUS 0x00
+#define TIMER_VALUE 0x04
+#define TIMER_CONTRL 0x10
+#define TIMER_CONFIG 0x20
+#define TIMER_DIV 0x24
+#define TIMER_INI 0x28
+
+#define GX6605S_STATUS_CLR BIT(0)
+#define GX6605S_CONTRL_RST BIT(0)
+#define GX6605S_CONTRL_START BIT(1)
+#define GX6605S_CONFIG_EN BIT(0)
+#define GX6605S_CONFIG_IRQ_EN BIT(1)
+
+static irqreturn_t gx6605s_timer_interrupt(int irq, void *dev)
+{
+ struct clock_event_device *ce = dev;
+ void __iomem *base = timer_of_base(to_timer_of(ce));
+
+ writel_relaxed(GX6605S_STATUS_CLR, base + TIMER_STATUS);
+
+ ce->event_handler(ce);
+
+ return IRQ_HANDLED;
+}
+
+static int gx6605s_timer_set_oneshot(struct clock_event_device *ce)
+{
+ void __iomem *base = timer_of_base(to_timer_of(ce));
+
+ /* reset and stop counter */
+ writel_relaxed(GX6605S_CONTRL_RST, base + TIMER_CONTRL);
+
+ /* enable with irq and start */
+ writel_relaxed(GX6605S_CONFIG_EN | GX6605S_CONFIG_IRQ_EN, base + TIMER_CONFIG);
+
+ return 0;
+}
+
+static int gx6605s_timer_set_next_event(unsigned long delta, struct clock_event_device *ce)
+{
+ void __iomem *base = timer_of_base(to_timer_of(ce));
+
+ /* use reset to pause timer */
+ writel_relaxed(GX6605S_CONTRL_RST, base + TIMER_CONTRL);
+
+ /* config next timeout value */
+ writel_relaxed(ULONG_MAX - delta, base + TIMER_INI);
+ writel_relaxed(GX6605S_CONTRL_START, base + TIMER_CONTRL);
+
+ return 0;
+}
+
+static int gx6605s_timer_shutdown(struct clock_event_device *ce)
+{
+ void __iomem *base = timer_of_base(to_timer_of(ce));
+
+ writel_relaxed(0, base + TIMER_CONTRL);
+ writel_relaxed(0, base + TIMER_CONFIG);
+
+ return 0;
+}
+
+static struct timer_of to = {
+ .flags = TIMER_OF_IRQ | TIMER_OF_BASE | TIMER_OF_CLOCK,
+ .clkevt = {
+ .rating = 300,
+ .features = CLOCK_EVT_FEAT_DYNIRQ |
+ CLOCK_EVT_FEAT_ONESHOT,
+ .set_state_shutdown = gx6605s_timer_shutdown,
+ .set_state_oneshot = gx6605s_timer_set_oneshot,
+ .set_next_event = gx6605s_timer_set_next_event,
+ .cpumask = cpu_possible_mask,
+ },
+ .of_irq = {
+ .handler = gx6605s_timer_interrupt,
+ .flags = IRQF_TIMER | IRQF_IRQPOLL,
+ },
+};
+
+static u64 notrace gx6605s_sched_clock_read(void)
+{
+ void __iomem *base;
+
+ base = timer_of_base(&to) + CLKSRC_OFFSET;
+
+ return (u64)readl_relaxed(base + TIMER_VALUE);
+}
+
+static void gx6605s_clkevt_init(void __iomem *base)
+{
+ writel_relaxed(0, base + TIMER_DIV);
+ writel_relaxed(0, base + TIMER_CONFIG);
+
+ clockevents_config_and_register(&to.clkevt, timer_of_rate(&to), 2, ULONG_MAX);
+}
+
+static int gx6605s_clksrc_init(void __iomem *base)
+{
+ writel_relaxed(0, base + TIMER_DIV);
+ writel_relaxed(0, base + TIMER_INI);
+
+ writel_relaxed(GX6605S_CONTRL_RST, base + TIMER_CONTRL);
+
+ writel_relaxed(GX6605S_CONFIG_EN, base + TIMER_CONFIG);
+
+ writel_relaxed(GX6605S_CONTRL_START, base + TIMER_CONTRL);
+
+ sched_clock_register(gx6605s_sched_clock_read, 32, timer_of_rate(&to));
+
+ return clocksource_mmio_init(base + TIMER_VALUE, "gx6605s", timer_of_rate(&to),
+ 200, 32, clocksource_mmio_readl_up);
+}
+
+static int __init gx6605s_timer_init(struct device_node *np)
+{
+ int ret;
+
+ /*
+ * The timer driver is for nationalchip gx6605s SOC and there are two same timer
+ * in gx6605s. We use one for clkevt and another for clksrc.
+ *
+ * The timer is mmio map to access, so we need give mmio addres in dts.
+ *
+ * It provides a 32bit countup timer and interrupt will be caused by count-overflow.
+ * So we need set-next-event by ULONG_MAX - delta in TIMER_INI reg.
+ *
+ * The counter at 0x0 offset is clock event.
+ * The counter at 0x40 offset is clock source.
+ * They are the same in hardware, just different used by driver.
+ */
+ ret = timer_of_init(np, &to);
+ if (ret)
+ return ret;
+
+ gx6605s_clkevt_init(timer_of_base(&to));
+
+ return gx6605s_clksrc_init(timer_of_base(&to) + CLKSRC_OFFSET);
+}
+TIMER_OF_DECLARE(csky_gx6605s_timer, "csky,gx6605s-timer", gx6605s_timer_init);
--
2.7.4
prev parent reply other threads:[~2018-09-24 23:44 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-09-24 14:34 [PATCH V5 00/30] C-SKY(csky) Linux Kernel Port Guo Ren
2018-09-24 14:36 ` [PATCH V5 01/30] csky: Build infrastructure Guo Ren
2018-09-24 14:36 ` [PATCH V5 02/30] csky: defconfig Guo Ren
2018-09-24 14:36 ` [PATCH V5 03/30] csky: Kernel booting Guo Ren
2018-09-24 14:36 ` [PATCH V5 04/30] csky: Exception handling and mm-fault Guo Ren
2018-09-24 14:36 ` [PATCH V5 05/30] csky: System Call Guo Ren
2018-09-24 14:36 ` [PATCH V5 06/30] csky: Cache and TLB routines Guo Ren
2018-09-25 7:24 ` Peter Zijlstra
2018-09-27 5:27 ` Guo Ren
2018-09-27 7:08 ` Peter Zijlstra
2018-09-27 8:11 ` Guo Ren
2018-09-27 9:01 ` Peter Zijlstra
2018-09-27 11:19 ` Guo Ren
2018-09-24 14:36 ` [PATCH V5 07/30] csky: MMU and page table management Guo Ren
2018-09-24 14:36 ` [PATCH V5 08/30] csky: Process management and Signal Guo Ren
2018-09-24 14:36 ` [PATCH V5 09/30] csky: VDSO and rt_sigreturn Guo Ren
2018-09-24 14:36 ` [PATCH V5 10/30] csky: IRQ handling Guo Ren
2018-09-24 14:36 ` [PATCH V5 11/30] csky: Atomic operations Guo Ren
2018-09-24 14:36 ` [PATCH V5 12/30] csky: ELF and module probe Guo Ren
2018-09-24 14:36 ` [PATCH V5 13/30] csky: Library functions Guo Ren
2018-09-24 14:36 ` [PATCH V5 14/30] csky: User access Guo Ren
2018-09-24 23:39 ` [PATCH V5 15/30] csky: Debug and Ptrace GDB Guo Ren
2018-09-24 23:39 ` [PATCH V5 16/30] csky: SMP support Guo Ren
2018-09-24 23:39 ` [PATCH V5 17/30] csky: Misc headers Guo Ren
2018-09-25 10:08 ` Andrea Parri
2018-09-25 10:45 ` Peter Zijlstra
2018-09-27 5:07 ` Guo Ren
2018-09-24 23:39 ` [PATCH V5 18/30] dt-bindings: csky CPU Bindings Guo Ren
2018-09-27 16:43 ` Rob Herring
2018-09-28 1:03 ` Guo Ren
2018-09-28 11:32 ` Rob Herring
2018-09-28 11:42 ` Guo Ren
2018-09-24 23:39 ` [PATCH V5 19/30] dt-bindings: Add vendor prefix for csky Guo Ren
2018-09-27 16:44 ` Rob Herring
2018-09-24 23:39 ` [PATCH V5 20/30] csky/dma: bugfix dma_sync_for_cpu/device Guo Ren
2018-09-24 23:39 ` [PATCH V5 21/30] csky: remove irq_mapping from smp.c Guo Ren
2018-09-24 23:39 ` [PATCH V5 22/30] irqchip: add C-SKY SMP interrupt controller Guo Ren
2018-09-24 23:39 ` [PATCH V5 23/30] dt-bindings: interrupt-controller: C-SKY SMP intc Guo Ren
2018-09-27 16:50 ` Rob Herring
2018-09-28 1:07 ` Guo Ren
2018-09-24 23:39 ` [PATCH V5 24/30] clocksource: add C-SKY SMP timer Guo Ren
2018-09-24 23:39 ` [PATCH V5 25/30] dt-bindings: timer: C-SKY Multi-processor timer Guo Ren
2018-09-27 17:35 ` Rob Herring
2018-09-24 23:39 ` [PATCH V5 26/30] MAINTAINERS: Add csky Guo Ren
2018-09-24 23:39 ` [PATCH V5 27/30] dt-bindings: interrupt-controller: C-SKY APB intc Guo Ren
2018-09-27 17:36 ` Rob Herring
2018-09-24 23:39 ` [PATCH V5 28/30] irqchip: add C-SKY APB bus interrupt controller Guo Ren
2018-09-24 23:39 ` [PATCH V5 29/30] dt-bindings: timer: gx6605s SOC timer Guo Ren
2018-09-24 23:39 ` Guo Ren [this message]
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