From: Dmitry Osipenko <digetx@gmail.com>
To: Stephen Boyd <sboyd@kernel.org>,
Jonathan Hunter <jonathanh@nvidia.com>,
Michael Turquette <mturquette@baylibre.com>,
Peter De Schrijver <pdeschrijver@nvidia.com>,
Prashant Gaikwad <pgaikwad@nvidia.com>,
Thierry Reding <thierry.reding@gmail.com>
Cc: linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2] clk: tegra: divider: Check UART's divider enable-bit state on rate's recalculation
Date: Thu, 14 Nov 2019 14:29:51 +0300 [thread overview]
Message-ID: <02df00b3-5e23-441f-b2d5-b84fdb411e98@gmail.com> (raw)
In-Reply-To: <20191113230303.726AE206E3@mail.kernel.org>
14.11.2019 02:03, Stephen Boyd пишет:
> Quoting Dmitry Osipenko (2019-10-29 17:48:13)
>> UART clock is divided using divisor values from DLM/DLL registers when
>> enable-bit is unset in clk register and clk's divider configuration isn't
>> taken onto account in this case. This doesn't cause any problems, but
>> let's add a check for the divider's enable-bit state, for consistency.
>>
>> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
>> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
>> ---
>
> Is this going to be picked up or should I just apply atop the tegra PR?
Looks like this patch missed the Tegra's PR by accident.
Stephen, I assume it will be easier if you could apply this patch atop.
The patch doesn't have any dependencies on any other patches, so it's
fine to apply it separately. Thanks in advance!
Thierry, please let us know if you have any objections.
next prev parent reply other threads:[~2019-11-14 11:29 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-30 0:48 [PATCH v2] clk: tegra: divider: Check UART's divider enable-bit state on rate's recalculation Dmitry Osipenko
2019-11-13 23:03 ` Stephen Boyd
2019-11-14 11:29 ` Dmitry Osipenko [this message]
2019-11-14 11:56 ` Thierry Reding
2019-11-14 12:10 ` Dmitry Osipenko
2019-11-15 21:36 ` Stephen Boyd
2019-11-14 11:54 ` Thierry Reding
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