From: Tim Chen <tim.c.chen@linux.intel.com>
To: Jiri Kosina <jikos@kernel.org>, Thomas Gleixner <tglx@linutronix.de>
Cc: Tim Chen <tim.c.chen@linux.intel.com>,
Tom Lendacky <thomas.lendacky@amd.com>,
Ingo Molnar <mingo@redhat.com>,
Peter Zijlstra <peterz@infradead.org>,
Josh Poimboeuf <jpoimboe@redhat.com>,
Andrea Arcangeli <aarcange@redhat.com>,
David Woodhouse <dwmw@amazon.co.uk>,
Andi Kleen <ak@linux.intel.com>,
Dave Hansen <dave.hansen@intel.com>,
Casey Schaufler <casey.schaufler@intel.com>,
Asit Mallick <asit.k.mallick@intel.com>,
Arjan van de Ven <arjan@linux.intel.com>,
Jon Masters <jcm@redhat.com>, Waiman Long <longman9394@gmail.com>,
linux-kernel@vger.kernel.org, x86@kernel.org
Subject: [Patch v5 10/16] x86/speculation: Turn on or off STIBP according to a task's TIF_STIBP
Date: Fri, 16 Nov 2018 17:53:53 -0800 [thread overview]
Message-ID: <05bbde92757997c1b57450f83c25541e02f8e376.1542418937.git.tim.c.chen@linux.intel.com> (raw)
In-Reply-To: <cover.1542418936.git.tim.c.chen@linux.intel.com>
In-Reply-To: <cover.1542418936.git.tim.c.chen@linux.intel.com>
If STIBP is used all the time, tasks that do not need STIBP
protection will get unnecessarily slowed down by STIBP.
To apply STIBP only to tasks that need it, a new task TIF_STIBP flag is
created. A x86 CPU uses STIBP only for tasks labeled with TIF_STIBP.
During context switch, this flag is checked and the STIBP bit in SPEC_CTRL
MSR is updated according to changes in this flag between previous and
next task.
Signed-off-by: Tim Chen <tim.c.chen@linux.intel.com>
---
arch/x86/include/asm/msr-index.h | 6 +++++-
arch/x86/include/asm/spec-ctrl.h | 12 ++++++++++++
arch/x86/include/asm/thread_info.h | 5 ++++-
arch/x86/kernel/process.c | 10 +++++++++-
4 files changed, 30 insertions(+), 3 deletions(-)
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 80f4a4f..501c9d3 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -41,7 +41,11 @@
#define MSR_IA32_SPEC_CTRL 0x00000048 /* Speculation Control */
#define SPEC_CTRL_IBRS (1 << 0) /* Indirect Branch Restricted Speculation */
-#define SPEC_CTRL_STIBP (1 << 1) /* Single Thread Indirect Branch Predictors */
+#define SPEC_CTRL_STIBP_SHIFT 1 /*
+ * Single Thread Indirect Branch
+ * Predictor (STIBP) bit
+ */
+#define SPEC_CTRL_STIBP (1 << SPEC_CTRL_STIBP_SHIFT) /* STIBP mask */
#define SPEC_CTRL_SSBD_SHIFT 2 /* Speculative Store Bypass Disable bit */
#define SPEC_CTRL_SSBD (1 << SPEC_CTRL_SSBD_SHIFT) /* Speculative Store Bypass Disable */
diff --git a/arch/x86/include/asm/spec-ctrl.h b/arch/x86/include/asm/spec-ctrl.h
index 8e2f841..b593779 100644
--- a/arch/x86/include/asm/spec-ctrl.h
+++ b/arch/x86/include/asm/spec-ctrl.h
@@ -53,12 +53,24 @@ static inline u64 ssbd_tif_to_spec_ctrl(u64 tifn)
return (tifn & _TIF_SSBD) >> (TIF_SSBD - SPEC_CTRL_SSBD_SHIFT);
}
+static inline u64 stibp_tif_to_spec_ctrl(u64 tifn)
+{
+ BUILD_BUG_ON(TIF_STIBP < SPEC_CTRL_STIBP_SHIFT);
+ return (tifn & _TIF_STIBP) >> (TIF_STIBP - SPEC_CTRL_STIBP_SHIFT);
+}
+
static inline unsigned long ssbd_spec_ctrl_to_tif(u64 spec_ctrl)
{
BUILD_BUG_ON(TIF_SSBD < SPEC_CTRL_SSBD_SHIFT);
return (spec_ctrl & SPEC_CTRL_SSBD) << (TIF_SSBD - SPEC_CTRL_SSBD_SHIFT);
}
+static inline unsigned long stibp_spec_ctrl_to_tif(u64 spec_ctrl)
+{
+ BUILD_BUG_ON(TIF_STIBP < SPEC_CTRL_STIBP_SHIFT);
+ return (spec_ctrl & SPEC_CTRL_STIBP) << (TIF_STIBP - SPEC_CTRL_STIBP_SHIFT);
+}
+
static inline u64 ssbd_tif_to_amd_ls_cfg(u64 tifn)
{
return (tifn & _TIF_SSBD) ? x86_amd_ls_cfg_ssbd_mask : 0ULL;
diff --git a/arch/x86/include/asm/thread_info.h b/arch/x86/include/asm/thread_info.h
index 2ff2a30..8736d23 100644
--- a/arch/x86/include/asm/thread_info.h
+++ b/arch/x86/include/asm/thread_info.h
@@ -83,6 +83,7 @@ struct thread_info {
#define TIF_SYSCALL_EMU 6 /* syscall emulation active */
#define TIF_SYSCALL_AUDIT 7 /* syscall auditing active */
#define TIF_SECCOMP 8 /* secure computing */
+#define TIF_STIBP 9 /* Single thread indirect branch speculation */
#define TIF_USER_RETURN_NOTIFY 11 /* notify kernel of userspace return */
#define TIF_UPROBE 12 /* breakpointed or singlestepping */
#define TIF_PATCH_PENDING 13 /* pending live patching update */
@@ -110,6 +111,7 @@ struct thread_info {
#define _TIF_SYSCALL_EMU (1 << TIF_SYSCALL_EMU)
#define _TIF_SYSCALL_AUDIT (1 << TIF_SYSCALL_AUDIT)
#define _TIF_SECCOMP (1 << TIF_SECCOMP)
+#define _TIF_STIBP (1 << TIF_STIBP)
#define _TIF_USER_RETURN_NOTIFY (1 << TIF_USER_RETURN_NOTIFY)
#define _TIF_UPROBE (1 << TIF_UPROBE)
#define _TIF_PATCH_PENDING (1 << TIF_PATCH_PENDING)
@@ -146,7 +148,8 @@ struct thread_info {
/* flags to check in __switch_to() */
#define _TIF_WORK_CTXSW \
- (_TIF_IO_BITMAP|_TIF_NOCPUID|_TIF_NOTSC|_TIF_BLOCKSTEP|_TIF_SSBD)
+ (_TIF_IO_BITMAP|_TIF_NOCPUID|_TIF_NOTSC|_TIF_BLOCKSTEP| \
+ _TIF_SSBD|_TIF_STIBP)
#define _TIF_WORK_CTXSW_PREV (_TIF_WORK_CTXSW|_TIF_USER_RETURN_NOTIFY)
#define _TIF_WORK_CTXSW_NEXT (_TIF_WORK_CTXSW)
diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c
index 74bef48..943e90d 100644
--- a/arch/x86/kernel/process.c
+++ b/arch/x86/kernel/process.c
@@ -406,6 +406,14 @@ static __always_inline void spec_ctrl_update_msr(unsigned long tifn)
if (static_cpu_has(X86_FEATURE_SSBD))
msr |= ssbd_tif_to_spec_ctrl(tifn);
+ /*
+ * Need STIBP defense against Spectre v2 attack
+ * if SMT is in use and enhanced IBRS is unsupported.
+ */
+ if (static_branch_likely(&cpu_smt_enabled) &&
+ !static_cpu_has(X86_FEATURE_USE_IBRS_ENHANCED))
+ msr |= stibp_tif_to_spec_ctrl(tifn);
+
wrmsrl(MSR_IA32_SPEC_CTRL, msr);
}
@@ -418,7 +426,7 @@ static __always_inline void spec_ctrl_update_msr(unsigned long tifn)
static __always_inline void __speculation_ctrl_update(unsigned long tifp,
unsigned long tifn)
{
- bool updmsr = false;
+ bool updmsr = !!((tifp ^ tifn) & _TIF_STIBP);
/* If TIF_SSBD is different, select the proper mitigation method */
if ((tifp ^ tifn) & _TIF_SSBD) {
--
2.9.4
next prev parent reply other threads:[~2018-11-17 2:27 UTC|newest]
Thread overview: 64+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-17 1:53 [Patch v5 00/16] Provide task property based options to enable Spectre v2 userspace-userspace protection Tim Chen
2018-11-17 1:53 ` [Patch v5 01/16] x86/speculation: Clean up spectre_v2_parse_cmdline() Tim Chen
2018-11-17 1:53 ` [Patch v5 02/16] x86/speculation: Remove unnecessary ret variable in cpu_show_common() Tim Chen
2018-11-17 1:53 ` [Patch v5 03/16] x86/speculation: Reorganize cpu_show_common() Tim Chen
2018-11-17 1:53 ` [Patch v5 04/16] x86/speculation: Add X86_FEATURE_USE_IBRS_ENHANCED Tim Chen
2018-11-17 1:53 ` [Patch v5 05/16] x86/speculation: Disable STIBP when enhanced IBRS is in use Tim Chen
2018-11-17 1:53 ` [Patch v5 06/16] x86/speculation: Rename SSBD update functions Tim Chen
2018-11-17 1:53 ` [Patch v5 07/16] x86/speculation: Reorganize speculation control MSRs update Tim Chen
2018-11-17 1:53 ` [Patch v5 08/16] smt: Create cpu_smt_enabled static key for SMT specific code Tim Chen
2018-11-19 12:58 ` Thomas Gleixner
2018-11-19 20:50 ` Tim Chen
2018-11-19 14:57 ` Peter Zijlstra
2018-11-19 18:08 ` Tim Chen
2018-11-19 19:03 ` Thomas Gleixner
2018-11-19 19:25 ` Tim Chen
2018-11-17 1:53 ` [Patch v5 09/16] x86/smt: Convert cpu_smt_control check to cpu_smt_enabled static key Tim Chen
2018-11-19 12:48 ` Thomas Gleixner
2018-11-19 12:59 ` Thomas Gleixner
2018-11-17 1:53 ` Tim Chen [this message]
2018-11-17 1:53 ` [Patch v5 11/16] x86/speculation: Add Spectre v2 app to app protection modes Tim Chen
2018-11-17 9:47 ` Jiri Kosina
2018-11-18 22:59 ` Jiri Kosina
2018-11-19 13:36 ` Thomas Gleixner
2018-11-19 13:49 ` Jiri Kosina
2018-11-19 13:51 ` Thomas Gleixner
2018-11-19 14:00 ` Jiri Kosina
2018-11-19 18:31 ` Tim Chen
2018-11-19 19:32 ` Andrea Arcangeli
2018-11-19 19:39 ` Jiri Kosina
2018-11-19 21:40 ` Andrea Arcangeli
2018-11-19 21:33 ` Dave Hansen
2018-11-19 23:16 ` Andrea Arcangeli
2018-11-19 23:25 ` Dave Hansen
2018-11-19 23:45 ` Andrea Arcangeli
2018-11-20 0:22 ` Thomas Gleixner
2018-11-19 13:32 ` Thomas Gleixner
2018-11-20 0:08 ` Tim Chen
2018-11-20 0:30 ` Thomas Gleixner
2018-11-20 1:14 ` Tim Chen
2018-11-20 1:17 ` Andi Kleen
2018-11-19 15:00 ` Thomas Gleixner
2018-11-19 18:27 ` Tim Chen
2018-11-19 18:31 ` Jiri Kosina
2018-11-19 20:21 ` Thomas Gleixner
2018-11-19 22:44 ` Tim Chen
2018-11-19 20:46 ` Thomas Gleixner
2018-11-19 20:55 ` Jiri Kosina
2018-11-19 21:12 ` Thomas Gleixner
2018-11-19 22:48 ` Tim Chen
2018-11-19 23:01 ` Thomas Gleixner
2018-11-19 23:23 ` Jiri Kosina
2018-11-20 0:00 ` Thomas Gleixner
2018-11-20 0:24 ` Tim Chen
2018-11-19 23:39 ` Dave Hansen
2018-11-19 23:49 ` Jiri Kosina
2018-11-20 0:02 ` Thomas Gleixner
2018-11-17 1:53 ` [Patch v5 12/16] x86/speculation: Create PRCTL interface to restrict indirect branch speculation Tim Chen
2018-11-17 9:53 ` Jiri Kosina
2018-11-19 18:29 ` Tim Chen
2018-11-17 1:53 ` [Patch v5 13/16] security: Update speculation restriction of a process when modifying its dumpability Tim Chen
2018-11-17 1:53 ` [Patch v5 14/16] x86/speculation: Use STIBP to restrict speculation on non-dumpable task Tim Chen
2018-11-17 1:53 ` [Patch v5 15/16] x86/speculation: Update comment on TIF_SSBD Tim Chen
2018-11-17 1:53 ` [Patch v5 16/16] x86: Group thread info flags by functionality Tim Chen
2018-11-17 9:34 ` [Patch v5 00/16] Provide task property based options to enable Spectre v2 userspace-userspace protection Jiri Kosina
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