From: Alan Cox <alan@lxorguk.ukuu.org.uk>
To: Christopher Wedgwood <cw@sgi.com>
Cc: Marcelo Tosatti <marcelo@conectiva.com.br>,
Alan Cox <alan@redhat.com>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
wildos@sgi.com
Subject: Re: [PATCH] (2.4.22-pre6 BK) New (IDE) driver: SGI IOC4
Date: 17 Jul 2003 13:26:27 +0100 [thread overview]
Message-ID: <1058444787.8620.42.camel@dhcp22.swansea.linux.org.uk> (raw)
In-Reply-To: <20030715222744.GA7478@taniwha.engr.sgi.com>
Ok the big problem I'm having with this code is understanding why most
of it even exists. Is this chip subtly different in some way I am
missing and so unable to use the generic PCI stuff or is most of the
copied code simply not needed.
As far as I can see the only "weirdness" it has is that the base
registers are off a non standard BAR. Thats something we already support
in the core IDE PCI code (see the cs5520 Kahlua driver in 2.6.0test)
Work was also done recently to allow clean wrapping of the generic DMA
stuff for devices that had to do custom setup around each IDE DMA (eg
HPT372N).
Basically - in what was is your controller not the same as generic MWDMA
capable IDE ?
prev parent reply other threads:[~2003-07-17 12:14 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2003-07-15 22:27 [PATCH] (2.4.22-pre6 BK) New (IDE) driver: SGI IOC4 Christopher Wedgwood
2003-07-15 23:47 ` Jeff Garzik
2003-07-16 0:13 ` Alan Cox
2003-07-17 12:26 ` Alan Cox [this message]
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