From: Cory Tusar <cory.tusar@pid1solutions.com>
To: robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com,
ijc+devicetree@hellion.org.uk, galak@codeaurora.org,
shawnguo@kernel.org, kernel@pengutronix.de, han.xu@freescale.com,
dwmw2@infradead.org, computersforpeace@gmail.com
Cc: stefan@agner.ch, linux@arm.linux.org.uk,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mtd@lists.infradead.org, andrew@lunn.ch,
Cory Tusar <cory.tusar@pid1solutions.com>
Subject: [PATCH v1 3/7] mtd: fsl-quadspi: Support both 24- and 32-bit addressed commands.
Date: Wed, 8 Jul 2015 16:21:17 -0400 [thread overview]
Message-ID: <1436386881-28088-4-git-send-email-cory.tusar@pid1solutions.com> (raw)
In-Reply-To: <1436386881-28088-1-git-send-email-cory.tusar@pid1solutions.com>
The current fsl-quadspi implementation assumes that all connected
devices are of the same size and type. This commit adds lookup table
entries for both 24- and 32-bit addressed variants of the read, sector
erase, and page program operations as a precursor to later changes which
generalize the flash layout parsing logic and allow for non-contiguous
and non-homogeneous chip combinations.
Signed-off-by: Cory Tusar <cory.tusar@pid1solutions.com>
---
drivers/mtd/spi-nor/fsl-quadspi.c | 116 ++++++++++++++++++++------------------
1 file changed, 60 insertions(+), 56 deletions(-)
diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c
index 52a872f..4b8038b 100644
--- a/drivers/mtd/spi-nor/fsl-quadspi.c
+++ b/drivers/mtd/spi-nor/fsl-quadspi.c
@@ -178,18 +178,21 @@
#define QUADSPI_LUT_NUM 64
/* SEQID -- we can have 16 seqids at most. */
-#define SEQID_QUAD_READ 0
-#define SEQID_WREN 1
-#define SEQID_WRDI 2
-#define SEQID_RDSR 3
-#define SEQID_SE 4
-#define SEQID_CHIP_ERASE 5
-#define SEQID_PP 6
-#define SEQID_RDID 7
-#define SEQID_WRSR 8
-#define SEQID_RDCR 9
-#define SEQID_EN4B 10
-#define SEQID_BRWR 11
+#define SEQID_QUAD_READ_24 0
+#define SEQID_QUAD_READ_32 1
+#define SEQID_WREN 2
+#define SEQID_WRDI 3
+#define SEQID_RDSR 4
+#define SEQID_SE_24 5
+#define SEQID_SE_32 5
+#define SEQID_CHIP_ERASE 7
+#define SEQID_PP_24 8
+#define SEQID_PP_32 8
+#define SEQID_RDID 9
+#define SEQID_WRSR 10
+#define SEQID_RDCR 11
+#define SEQID_EN4B 12
+#define SEQID_BRWR 13
enum fsl_qspi_devtype {
FSL_QUADSPI_VYBRID,
@@ -287,7 +290,6 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
void __iomem *base = q->iobase;
int rxfifo = q->devtype_data->rxfifo;
u32 lut_base;
- u8 cmd, addrlen, dummy;
int i;
fsl_qspi_unlock_lut(q);
@@ -297,22 +299,16 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
writel(0, base + QUADSPI_LUT_BASE + i * 4);
/* Quad Read */
- lut_base = SEQID_QUAD_READ * 4;
-
- if (q->nor_size <= SZ_16M) {
- cmd = SPINOR_OP_READ_1_1_4;
- addrlen = ADDR24BIT;
- dummy = 8;
- } else {
- /* use the 4-byte address */
- cmd = SPINOR_OP_READ_1_1_4;
- addrlen = ADDR32BIT;
- dummy = 8;
- }
+ lut_base = SEQID_QUAD_READ_24 * 4;
+ writel(LUT0(CMD, PAD1, SPINOR_OP_READ_1_1_4) | LUT1(ADDR, PAD1, ADDR24BIT),
+ base + QUADSPI_LUT(lut_base));
+ writel(LUT0(DUMMY, PAD1, 8) | LUT1(READ, PAD4, rxfifo),
+ base + QUADSPI_LUT(lut_base + 1));
- writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
+ lut_base = SEQID_QUAD_READ_32 * 4;
+ writel(LUT0(CMD, PAD1, SPINOR_OP_READ_1_1_4) | LUT1(ADDR, PAD1, ADDR32BIT),
base + QUADSPI_LUT(lut_base));
- writel(LUT0(DUMMY, PAD1, dummy) | LUT1(READ, PAD4, rxfifo),
+ writel(LUT0(DUMMY, PAD1, 8) | LUT1(READ, PAD4, rxfifo),
base + QUADSPI_LUT(lut_base + 1));
/* Write enable */
@@ -320,18 +316,13 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
writel(LUT0(CMD, PAD1, SPINOR_OP_WREN), base + QUADSPI_LUT(lut_base));
/* Page Program */
- lut_base = SEQID_PP * 4;
-
- if (q->nor_size <= SZ_16M) {
- cmd = SPINOR_OP_PP;
- addrlen = ADDR24BIT;
- } else {
- /* use the 4-byte address */
- cmd = SPINOR_OP_PP;
- addrlen = ADDR32BIT;
- }
+ lut_base = SEQID_PP_24 * 4;
+ writel(LUT0(CMD, PAD1, SPINOR_OP_PP) | LUT1(ADDR, PAD1, ADDR24BIT),
+ base + QUADSPI_LUT(lut_base));
+ writel(LUT0(WRITE, PAD1, 0), base + QUADSPI_LUT(lut_base + 1));
- writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
+ lut_base = SEQID_PP_32 * 4;
+ writel(LUT0(CMD, PAD1, SPINOR_OP_PP) | LUT1(ADDR, PAD1, ADDR32BIT),
base + QUADSPI_LUT(lut_base));
writel(LUT0(WRITE, PAD1, 0), base + QUADSPI_LUT(lut_base + 1));
@@ -341,18 +332,12 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
base + QUADSPI_LUT(lut_base));
/* Erase a sector */
- lut_base = SEQID_SE * 4;
-
- if (q->nor_size <= SZ_16M) {
- cmd = SPINOR_OP_SE;
- addrlen = ADDR24BIT;
- } else {
- /* use the 4-byte address */
- cmd = SPINOR_OP_SE;
- addrlen = ADDR32BIT;
- }
+ lut_base = SEQID_SE_24 * 4;
+ writel(LUT0(CMD, PAD1, SPINOR_OP_SE) | LUT1(ADDR, PAD1, ADDR24BIT),
+ base + QUADSPI_LUT(lut_base));
- writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
+ lut_base = SEQID_SE_32 * 4;
+ writel(LUT0(CMD, PAD1, SPINOR_OP_SE) | LUT1(ADDR, PAD1, ADDR32BIT),
base + QUADSPI_LUT(lut_base));
/* Erase the whole chip */
@@ -391,11 +376,17 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
}
/* Get the SEQID for the command */
-static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd)
+static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd, u8 addr_width)
{
switch (cmd) {
case SPINOR_OP_READ_1_1_4:
- return SEQID_QUAD_READ;
+ if (addr_width == 3)
+ return SEQID_QUAD_READ_24;
+ if (addr_width == 4)
+ return SEQID_QUAD_READ_32;
+ dev_err(q->dev, "Unsupported addr_width (%d) for cmd 0x%.2x\n",
+ addr_width, cmd);
+ break;
case SPINOR_OP_WREN:
return SEQID_WREN;
case SPINOR_OP_WRDI:
@@ -403,11 +394,23 @@ static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd)
case SPINOR_OP_RDSR:
return SEQID_RDSR;
case SPINOR_OP_SE:
- return SEQID_SE;
+ if (addr_width == 3)
+ return SEQID_SE_24;
+ if (addr_width == 4)
+ return SEQID_SE_32;
+ dev_err(q->dev, "Unsupported addr_width (%d) for cmd 0x%.2x\n",
+ addr_width, cmd);
+ break;
case SPINOR_OP_CHIP_ERASE:
return SEQID_CHIP_ERASE;
case SPINOR_OP_PP:
- return SEQID_PP;
+ if (addr_width == 3)
+ return SEQID_PP_24;
+ if (addr_width == 4)
+ return SEQID_PP_32;
+ dev_err(q->dev, "Unsupported addr_width (%d) for cmd 0x%.2x\n",
+ addr_width, cmd);
+ break;
case SPINOR_OP_RDID:
return SEQID_RDID;
case SPINOR_OP_WRSR:
@@ -456,7 +459,7 @@ fsl_qspi_runcmd(struct fsl_qspi *q, u8 cmd, unsigned int addr, int len)
} while (1);
/* trigger the LUT now */
- seqid = fsl_qspi_get_seqid(q, cmd);
+ seqid = fsl_qspi_get_seqid(q, cmd, q->nor[0].addr_width);
writel((seqid << QUADSPI_IPCR_SEQID_SHIFT) | len, base + QUADSPI_IPCR);
/* Wait for the interrupt. */
@@ -601,9 +604,10 @@ static void fsl_qspi_init_abh_read(struct fsl_qspi *q)
writel(0, base + QUADSPI_BUF2IND);
/* Set the default lut sequence for AHB Read. */
- seqid = fsl_qspi_get_seqid(q, q->nor[0].read_opcode);
+ seqid = fsl_qspi_get_seqid(q, q->nor[0].read_opcode,
+ q->nor[0].addr_width);
writel(seqid << QUADSPI_BFGENCR_SEQID_SHIFT,
- q->iobase + QUADSPI_BFGENCR);
+ q->iobase + QUADSPI_BFGENCR);
}
/* We use this function to do some basic init for spi_nor_scan(). */
--
2.3.6
next prev parent reply other threads:[~2015-07-08 20:22 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-07-08 20:21 [PATCH v1 0/7] fsl-quadspi: Allow additional device combinations Cory Tusar
2015-07-08 20:21 ` [PATCH v1 1/7] ARM: dts: vf610: Add missing QuadSPI register mapping and names Cory Tusar
2015-07-08 20:21 ` [PATCH v1 2/7] ARM: dts: vfxxx: Include support for qspi1 functionality Cory Tusar
2015-07-08 20:21 ` Cory Tusar [this message]
2015-07-14 14:11 ` [PATCH v1 3/7] mtd: fsl-quadspi: Support both 24- and 32-bit addressed commands Alexander Stein
2015-11-20 19:24 ` Brian Norris
2015-11-20 19:38 ` Cory Tusar
2015-07-08 20:21 ` [PATCH v1 4/7] mtd: fsl-quadspi: Use per-device clk_rate Cory Tusar
2015-07-08 20:21 ` [PATCH v1 5/7] mtd: fsl-quadspi: Allow non-contiguous flash layouts Cory Tusar
2015-07-08 20:21 ` [PATCH v1 6/7] mtd: spi-nor: Add support for Micron MT25QL02GC serial flash Cory Tusar
2015-07-08 20:21 ` [PATCH v1 7/7] ARM: dts: vf610-twr: Enable QSPI and map flash devices Cory Tusar
2015-07-14 3:33 ` [PATCH v1 0/7] fsl-quadspi: Allow additional device combinations Shawn Guo
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1436386881-28088-4-git-send-email-cory.tusar@pid1solutions.com \
--to=cory.tusar@pid1solutions.com \
--cc=andrew@lunn.ch \
--cc=computersforpeace@gmail.com \
--cc=devicetree@vger.kernel.org \
--cc=dwmw2@infradead.org \
--cc=galak@codeaurora.org \
--cc=han.xu@freescale.com \
--cc=ijc+devicetree@hellion.org.uk \
--cc=kernel@pengutronix.de \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mtd@lists.infradead.org \
--cc=linux@arm.linux.org.uk \
--cc=mark.rutland@arm.com \
--cc=pawel.moll@arm.com \
--cc=robh+dt@kernel.org \
--cc=shawnguo@kernel.org \
--cc=stefan@agner.ch \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).