From: Girish Mahadevan <girishm@codeaurora.org>
To: broonie@kernel.org, linux-spi@vger.kernel.org,
linux-kernel@vger.kernel.org
Cc: sboyd@codeaurora.org, sdharia@codeaurora.org,
girishm@codeaurora.org, linux-arm-msm@vger.kernel.org
Subject: [PATCH RFCv1 1/1] spi: Expand tx_nbits/rx_nbits to add 8-bit transfer
Date: Wed, 13 Jul 2016 13:34:37 -0600 [thread overview]
Message-ID: <1468438477-18883-2-git-send-email-girishm@codeaurora.org> (raw)
In-Reply-To: <1468438477-18883-1-git-send-email-girishm@codeaurora.org>
Expand the tx_nbits/rx_nbits member of the spi_transfer struct to a 4 bit
value to allow specifying 8 bit transfers (SPI_NBITS_OCTO).
Change-Id: I0b7ab41b2caa8495da431944ccbc0b90942d5dd9
Signed-off-by: Girish Mahadevan <girishm@codeaurora.org>
---
include/linux/spi/spi.h | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
index 857a9a1..45b958a 100644
--- a/include/linux/spi/spi.h
+++ b/include/linux/spi/spi.h
@@ -717,10 +717,11 @@ extern void spi_res_release(struct spi_master *master,
* by the results of previous messages and where the whole transaction
* ends when the chipselect goes intactive.
*
- * When SPI can transfer in 1x,2x or 4x. It can get this transfer information
+ * When SPI can transfer in 1x,2x,4x or 8x. It can get this transfer information
* from device through @tx_nbits and @rx_nbits. In Bi-direction, these
* two should both be set. User can set transfer mode with SPI_NBITS_SINGLE(1x)
- * SPI_NBITS_DUAL(2x) and SPI_NBITS_QUAD(4x) to support these three transfer.
+ * SPI_NBITS_DUAL(2x) SPI_NBITS_QUAD(4x) and SPI_NBITS_OCTO(8x) to support
+ * these four transfers.
*
* The code that submits an spi_message (and its spi_transfers)
* to the lower layers is responsible for managing its memory.
@@ -744,11 +745,12 @@ struct spi_transfer {
struct sg_table rx_sg;
unsigned cs_change:1;
- unsigned tx_nbits:3;
- unsigned rx_nbits:3;
+ unsigned tx_nbits:4;
+ unsigned rx_nbits:4;
#define SPI_NBITS_SINGLE 0x01 /* 1bit transfer */
#define SPI_NBITS_DUAL 0x02 /* 2bits transfer */
#define SPI_NBITS_QUAD 0x04 /* 4bits transfer */
+#define SPI_NBITS_OCTO 0x08 /* 4bits transfer */
u8 bits_per_word;
u16 delay_usecs;
u32 speed_hz;
--
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project
next prev parent reply other threads:[~2016-07-13 19:35 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-07-13 19:34 [PATCH RFCv1 0/1] Update struct spi_transfer to specify 8x bit transfers Girish Mahadevan
2016-07-13 19:34 ` Girish Mahadevan [this message]
2016-08-05 17:57 ` [PATCH RFCv1 1/1] spi: Expand tx_nbits/rx_nbits to add 8-bit transfer Mark Brown
2016-07-14 13:30 ` [PATCH RFCv1 0/1] Update struct spi_transfer to specify 8x bit transfers Mark Brown
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1468438477-18883-2-git-send-email-girishm@codeaurora.org \
--to=girishm@codeaurora.org \
--cc=broonie@kernel.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-spi@vger.kernel.org \
--cc=sboyd@codeaurora.org \
--cc=sdharia@codeaurora.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).