From: <sean.wang@mediatek.com>
To: <rjw@rjwysocki.net>, <viresh.kumar@linaro.org>,
<robh+dt@kernel.org>, <matthias.bgg@gmail.com>,
<mark.rutland@arm.com>, <mturquette@baylibre.com>,
<jamesjj.liao@mediatek.com>, <p.zabel@pengutronix.de>,
<shunli.wang@mediatek.com>, <erin.lo@mediatek.com>,
<jdelvare@suse.de>, <devicetree@vger.kernel.org>,
<linux-mediatek@lists.infradead.org>, <linux-pm@vger.kernel.org>,
<linux-clk@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>
Cc: <linux-kernel@vger.kernel.org>,
Sean Wang <sean.wang@mediatek.com>,
Pi-Cheng Chen <pi-cheng.chen@linaro.org>
Subject: [PATCH 2/6] clk: mediatek: export cpu multiplexer clock for MT2701/MT7623 SoCs
Date: Fri, 5 May 2017 23:26:10 +0800 [thread overview]
Message-ID: <1493997974-17699-3-git-send-email-sean.wang@mediatek.com> (raw)
In-Reply-To: <1493997974-17699-1-git-send-email-sean.wang@mediatek.com>
From: Sean Wang <sean.wang@mediatek.com>
The patch enables CPU multiplexer clock on MT2701/MT7623 SoC which fixes
up cpufreq driver fails at acquiring intermediate clock source when driver
probe is called.
Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
---
drivers/clk/mediatek/clk-mt2701.c | 8 ++++++++
include/dt-bindings/clock/mt2701-clk.h | 3 ++-
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c
index 6f26e6a..9598889 100644
--- a/drivers/clk/mediatek/clk-mt2701.c
+++ b/drivers/clk/mediatek/clk-mt2701.c
@@ -20,6 +20,7 @@
#include "clk-mtk.h"
#include "clk-gate.h"
+#include "clk-cpumux.h"
#include <dt-bindings/clock/mt2701-clk.h>
@@ -493,6 +494,10 @@ static const char * const cpu_parents[] = {
"mmpll"
};
+static const struct mtk_composite cpu_muxes[] __initconst = {
+ MUX(CLK_INFRA_CPUSEL, "infra_cpu_sel", cpu_parents, 0x0000, 2, 2),
+};
+
static const struct mtk_composite top_muxes[] = {
MUX_GATE_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
0x0040, 0, 3, 7, CLK_IS_CRITICAL),
@@ -759,6 +764,9 @@ static void mtk_infrasys_init_early(struct device_node *node)
mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
infra_clk_data);
+ mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes),
+ infra_clk_data);
+
r = of_clk_add_provider(node, of_clk_src_onecell_get, infra_clk_data);
if (r)
pr_err("%s(): could not register clock provider: %d\n",
diff --git a/include/dt-bindings/clock/mt2701-clk.h b/include/dt-bindings/clock/mt2701-clk.h
index 2062c67..551f760 100644
--- a/include/dt-bindings/clock/mt2701-clk.h
+++ b/include/dt-bindings/clock/mt2701-clk.h
@@ -221,7 +221,8 @@
#define CLK_INFRA_PMICWRAP 17
#define CLK_INFRA_DDCCI 18
#define CLK_INFRA_CLK_13M 19
-#define CLK_INFRA_NR 20
+#define CLK_INFRA_CPUSEL 20
+#define CLK_INFRA_NR 21
/* PERICFG */
--
2.7.4
next prev parent reply other threads:[~2017-05-05 15:27 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-05-05 15:26 [PATCH 0/6] some fixups for Mediatek cpufreq driver sean.wang
2017-05-05 15:26 ` [PATCH 1/6] clk: mediatek: add missing cpu mux causing Mediatek cpufreq can't work sean.wang
2017-05-25 7:30 ` Sean Wang
2017-06-20 1:07 ` Stephen Boyd
2017-05-05 15:26 ` sean.wang [this message]
2017-06-20 1:07 ` [PATCH 2/6] clk: mediatek: export cpu multiplexer clock for MT2701/MT7623 SoCs Stephen Boyd
2017-05-05 15:26 ` [PATCH 3/6] clk: mediatek: export cpu multiplexer clock for MT8173 SoCs sean.wang
2017-06-20 1:07 ` Stephen Boyd
2017-05-05 15:26 ` [PATCH 4/6] cpufreq: mediatek: Add support of cpufreq to MT2701/MT7623 SoC sean.wang
2017-05-06 8:00 ` Jean Delvare
2017-05-08 6:09 ` Sean Wang
2017-05-05 15:26 ` [PATCH 5/6] dt-bindings: cpufreq: move Mediatek cpufreq dt-bindings document to proper place sean.wang
2017-05-08 4:18 ` Viresh Kumar
2017-05-08 6:19 ` Sean Wang
2017-05-08 7:08 ` Viresh Kumar
2017-05-05 15:26 ` [PATCH 6/6] dt-bindings: cpufreq: enhance Mediatek cpufreq dt-binding document sean.wang
2017-05-08 4:20 ` Viresh Kumar
2017-05-08 6:58 ` Sean Wang
2017-05-08 7:06 ` Viresh Kumar
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