From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org, will.deacon@arm.com,
marc.zyngier@arm.com, mark.rutland@arm.com, sudeep.holla@arm.com,
mathieu.poirier@linaro.org, Jonathan.Cameron@huawei.com,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Rob Herring <robh@kernel.org>
Subject: [PATCH v3 5/6] dt-bindings: Document devicetree binding for ARM DSU PMU
Date: Thu, 27 Jul 2017 16:10:17 +0100 [thread overview]
Message-ID: <1501168218-26741-6-git-send-email-suzuki.poulose@arm.com> (raw)
In-Reply-To: <1501168218-26741-1-git-send-email-suzuki.poulose@arm.com>
This patch documents the devicetree bindings for ARM DSU PMU.
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Rob Herring <robh@kernel.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
.../devicetree/bindings/arm/arm-dsu-pmu.txt | 27 ++++++++++++++++++++++
1 file changed, 27 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt
diff --git a/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt b/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt
new file mode 100644
index 0000000..b9935ac
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt
@@ -0,0 +1,27 @@
+* ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU)
+
+ARM DyanmIQ Shared Unit (DSU) integrates one or more CPU cores
+with a shared L3 memory system, control logic and external interfaces to
+form a multicore cluster. The PMU enables to gather various statistics on
+the operations of the DSU. The PMU provides independent 32bit counters that
+can count any of the supported events, along with a 64bit cycle counter.
+The PMU is accessed via CPU system registers and has no MMIO component.
+
+** DSU PMU required properties:
+
+- compatible : should be one of :
+
+ "arm,dsu-pmu"
+
+- interrupts : Exactly 1 SPI must be listed.
+
+- cpus : List of phandles for the CPUs connected to this DSU instance.
+
+
+** Example:
+
+dsu_pmu@0 {
+ compatible = "arm,dsu-pmu";
+ interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>;
+ cpus = <&cpu_0>, <&cpu_1>;
+};
--
2.7.5
next prev parent reply other threads:[~2017-07-27 15:10 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-07-27 15:10 [PATCH v3 0/6] perf: Support for ARM DynamIQ Shared Unit PMU Suzuki K Poulose
2017-07-27 15:10 ` [PATCH v3 1/6] perf: Export perf_event_update_userpage Suzuki K Poulose
2017-07-27 15:10 ` [PATCH v3 2/6] of: Add helper for mapping device node to logical CPU number Suzuki K Poulose
2017-07-27 15:48 ` Rob Herring
2017-07-27 16:27 ` Suzuki K Poulose
2017-07-27 15:10 ` [PATCH v3 3/6] coresight: of: Use of_device_node_get_cpu helper Suzuki K Poulose
2017-07-27 15:10 ` [PATCH v3 4/6] irqchip: gic-v3: " Suzuki K Poulose
2017-07-27 15:10 ` Suzuki K Poulose [this message]
2017-07-27 15:52 ` [PATCH v3 5/6] dt-bindings: Document devicetree binding for ARM DSU PMU Rob Herring
2017-07-27 16:09 ` Suzuki K Poulose
2017-07-27 15:10 ` [PATCH v3 6/6] perf: ARM DynamIQ Shared Unit PMU support Suzuki K Poulose
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