From: Erin Lo <erin.lo@mediatek.com>
To: Matthias Brugger <matthias.bgg@gmail.com>,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Thomas Gleixner <tglx@linutronix.de>,
Jason Cooper <jason@lakedaemon.net>,
Marc Zyngier <marc.zyngier@arm.com>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Stephen Boyd <sboyd@codeaurora.org>
Cc: <devicetree@vger.kernel.org>,
srv_heupstream <srv_heupstream@mediatek.com>,
<linux-kernel@vger.kernel.org>, <linux-serial@vger.kernel.org>,
<linux-mediatek@lists.infradead.org>,
<linux-arm-kernel@lists.infradead.org>,
<yingjoe.chen@mediatek.com>, <erin.lo@mediatek.com>,
<mars.cheng@mediatek.com>, <eddie.huang@mediatek.com>,
<linux-clk@vger.kernel.org>, Weiyi Lu <weiyi.lu@mediatek.com>
Subject: [PATCH v4 06/10] clk: mediatek: Add flags support for mtk_gate data
Date: Tue, 31 Jul 2018 13:38:03 +0800 [thread overview]
Message-ID: <1533015487-60189-7-git-send-email-erin.lo@mediatek.com> (raw)
In-Reply-To: <1533015487-60189-1-git-send-email-erin.lo@mediatek.com>
From: Weiyi Lu <weiyi.lu@mediatek.com>
On some Mediatek platforms, there are critical clocks of
clock gate type.
To register clock gate with flags CLK_IS_CRITICAL,
we need to add the flags field in mtk_gate data and register APIs.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Signed-off-by: Erin Lo <erin.lo@mediatek.com>
---
drivers/clk/mediatek/clk-gate.c | 5 +++--
drivers/clk/mediatek/clk-gate.h | 3 ++-
drivers/clk/mediatek/clk-mtk.c | 3 ++-
drivers/clk/mediatek/clk-mtk.h | 1 +
4 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/mediatek/clk-gate.c b/drivers/clk/mediatek/clk-gate.c
index 934bf0e..25d25c3 100644
--- a/drivers/clk/mediatek/clk-gate.c
+++ b/drivers/clk/mediatek/clk-gate.c
@@ -157,7 +157,8 @@ struct clk *mtk_clk_register_gate(
int clr_ofs,
int sta_ofs,
u8 bit,
- const struct clk_ops *ops)
+ const struct clk_ops *ops,
+ unsigned int flags)
{
struct mtk_clk_gate *cg;
struct clk *clk;
@@ -168,7 +169,7 @@ struct clk *mtk_clk_register_gate(
return ERR_PTR(-ENOMEM);
init.name = name;
- init.flags = CLK_SET_RATE_PARENT;
+ init.flags = flags | CLK_SET_RATE_PARENT;
init.parent_names = parent_name ? &parent_name : NULL;
init.num_parents = parent_name ? 1 : 0;
init.ops = ops;
diff --git a/drivers/clk/mediatek/clk-gate.h b/drivers/clk/mediatek/clk-gate.h
index 72ef89b..631cd3a 100644
--- a/drivers/clk/mediatek/clk-gate.h
+++ b/drivers/clk/mediatek/clk-gate.h
@@ -47,6 +47,7 @@ struct clk *mtk_clk_register_gate(
int clr_ofs,
int sta_ofs,
u8 bit,
- const struct clk_ops *ops);
+ const struct clk_ops *ops,
+ unsigned int flags);
#endif /* __DRV_CLK_GATE_H */
diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
index 50becd0..15310f8 100644
--- a/drivers/clk/mediatek/clk-mtk.c
+++ b/drivers/clk/mediatek/clk-mtk.c
@@ -131,7 +131,8 @@ int mtk_clk_register_gates(struct device_node *node,
gate->regs->set_ofs,
gate->regs->clr_ofs,
gate->regs->sta_ofs,
- gate->shift, gate->ops);
+ gate->shift, gate->ops,
+ gate->flags);
if (IS_ERR(clk)) {
pr_err("Failed to register clk %s: %ld\n",
diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index 61693f6..c3285ff 100644
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -217,6 +217,7 @@ struct mtk_gate {
const struct mtk_gate_regs *regs;
int shift;
const struct clk_ops *ops;
+ unsigned int flags;
};
int mtk_clk_register_gates(struct device_node *node,
--
1.9.1
next prev parent reply other threads:[~2018-07-31 5:40 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-31 5:37 [PATCH v4 00/10] Add basic and clock support for Mediatek MT8183 SoC Erin Lo
2018-07-31 5:37 ` [PATCH v4 01/10] dt-bindings: arm: Add bindings for Mediatek MT8183 SoC Platform Erin Lo
2018-07-31 5:37 ` [PATCH v4 02/10] dt-bindings: mtk-sysirq: Add compatible for Mediatek MT8183 Erin Lo
2018-07-31 5:38 ` [PATCH v4 03/10] arm64: dts: Add Mediatek SoC MT8183 and evaluation board dts and Makefile Erin Lo
2018-07-31 6:21 ` Marc Zyngier
2018-08-03 12:52 ` Matthias Brugger
2018-07-31 5:38 ` [PATCH v4 04/10] dt-bindings: ARM: Mediatek: Document bindings for MT8183 Erin Lo
2018-07-31 19:22 ` Rob Herring
2018-07-31 5:38 ` [PATCH v4 05/10] clk: mediatek: Add dt-bindings for MT8183 clocks Erin Lo
2018-07-31 19:24 ` Rob Herring
2018-07-31 5:38 ` Erin Lo [this message]
2018-07-31 5:38 ` [PATCH v4 07/10] clk: mediatek: Add MT8183 clock support Erin Lo
2018-07-31 5:38 ` [PATCH v4 08/10] arm64: dts: mt8183: Add clock controller device nodes Erin Lo
2018-07-31 5:38 ` [PATCH v4 09/10] dt-bindings: serial: Add compatible for Mediatek MT8183 Erin Lo
2018-07-31 5:38 ` [PATCH v4 10/10] dts: arm64: mt8183: add uart node Erin Lo
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