linux-kernel.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
From: Julien Thierry <julien.thierry@arm.com>
To: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org, daniel.thompson@linaro.org,
	joel@joelfernandes.org, marc.zyngier@arm.com,
	christoffer.dall@arm.com, james.morse@arm.com,
	catalin.marinas@arm.com, will.deacon@arm.com,
	mark.rutland@arm.com, Julien Thierry <julien.thierry@arm.com>,
	Arnd Bergmann <arnd@arndb.de>,
	linux-arch@vger.kernel.org, stable@vger.kernel.org
Subject: [PATCH v9 01/26] arm64: Fix HCR.TGE status for NMI contexts
Date: Mon, 21 Jan 2019 15:33:20 +0000	[thread overview]
Message-ID: <1548084825-8803-2-git-send-email-julien.thierry@arm.com> (raw)
In-Reply-To: <1548084825-8803-1-git-send-email-julien.thierry@arm.com>

When using VHE, the host needs to clear HCR_EL2.TGE bit in order
to interract with guest TLBs, switching from EL2&0 translation regime
to EL1&0.

However, some non-maskable asynchronous event could happen while TGE is
cleared like SDEI. Because of this address translation operations
relying on EL2&0 translation regime could fail (tlb invalidation,
userspace access, ...).

Fix this by properly setting HCR_EL2.TGE when entering NMI context and
clear it if necessary when returning to the interrupted context.

Signed-off-by: Julien Thierry <julien.thierry@arm.com>
Suggested-by: Marc Zyngier <marc.zyngier@arm.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: James Morse <james.morse@arm.com>
Cc: linux-arch@vger.kernel.org
Cc: stable@vger.kernel.org
---
 arch/arm64/include/asm/hardirq.h | 28 ++++++++++++++++++++++++++++
 arch/arm64/kernel/irq.c          |  3 +++
 include/linux/hardirq.h          |  7 +++++++
 3 files changed, 38 insertions(+)

diff --git a/arch/arm64/include/asm/hardirq.h b/arch/arm64/include/asm/hardirq.h
index 1473fc2..94b7481 100644
--- a/arch/arm64/include/asm/hardirq.h
+++ b/arch/arm64/include/asm/hardirq.h
@@ -19,6 +19,7 @@
 #include <linux/cache.h>
 #include <linux/threads.h>
 #include <asm/irq.h>
+#include <asm/kvm_arm.h>
 
 #define NR_IPI	7
 
@@ -37,6 +38,33 @@
 
 #define __ARCH_IRQ_EXIT_IRQS_DISABLED	1
 
+struct nmi_ctx {
+	u64 hcr;
+};
+
+DECLARE_PER_CPU(struct nmi_ctx, nmi_contexts);
+
+#define arch_nmi_enter()							\
+	do {									\
+		if (is_kernel_in_hyp_mode()) {					\
+			struct nmi_ctx *nmi_ctx = this_cpu_ptr(&nmi_contexts);	\
+			nmi_ctx->hcr = read_sysreg(hcr_el2);			\
+			if (!(nmi_ctx->hcr & HCR_TGE)) {			\
+				write_sysreg(nmi_ctx->hcr | HCR_TGE, hcr_el2);	\
+				isb();						\
+			}							\
+		}								\
+	} while (0)
+
+#define arch_nmi_exit()								\
+	do {									\
+		if (is_kernel_in_hyp_mode()) {					\
+			struct nmi_ctx *nmi_ctx = this_cpu_ptr(&nmi_contexts);	\
+			if (!(nmi_ctx->hcr & HCR_TGE))				\
+				write_sysreg(nmi_ctx->hcr, hcr_el2);		\
+		}								\
+	} while (0)
+
 static inline void ack_bad_irq(unsigned int irq)
 {
 	extern unsigned long irq_err_count;
diff --git a/arch/arm64/kernel/irq.c b/arch/arm64/kernel/irq.c
index 780a12f..92fa817 100644
--- a/arch/arm64/kernel/irq.c
+++ b/arch/arm64/kernel/irq.c
@@ -33,6 +33,9 @@
 
 unsigned long irq_err_count;
 
+/* Only access this in an NMI enter/exit */
+DEFINE_PER_CPU(struct nmi_ctx, nmi_contexts);
+
 DEFINE_PER_CPU(unsigned long *, irq_stack_ptr);
 
 int arch_show_interrupts(struct seq_file *p, int prec)
diff --git a/include/linux/hardirq.h b/include/linux/hardirq.h
index 0fbbcdf..da0af63 100644
--- a/include/linux/hardirq.h
+++ b/include/linux/hardirq.h
@@ -60,8 +60,14 @@ static inline void rcu_nmi_exit(void)
  */
 extern void irq_exit(void);
 
+#ifndef arch_nmi_enter
+#define arch_nmi_enter()	do { } while (0)
+#define arch_nmi_exit()		do { } while (0)
+#endif
+
 #define nmi_enter()						\
 	do {							\
+		arch_nmi_enter();				\
 		printk_nmi_enter();				\
 		lockdep_off();					\
 		ftrace_nmi_enter();				\
@@ -80,6 +86,7 @@ static inline void rcu_nmi_exit(void)
 		ftrace_nmi_exit();				\
 		lockdep_on();					\
 		printk_nmi_exit();				\
+		arch_nmi_exit();				\
 	} while (0)
 
 #endif /* LINUX_HARDIRQ_H */
-- 
1.9.1


  reply	other threads:[~2019-01-21 15:34 UTC|newest]

Thread overview: 81+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-01-21 15:33 [PATCH v9 00/26] arm64: provide pseudo NMI with GICv3 Julien Thierry
2019-01-21 15:33 ` Julien Thierry [this message]
2019-01-28 11:48   ` [PATCH v9 01/26] arm64: Fix HCR.TGE status for NMI contexts James Morse
2019-01-28 15:42     ` Julien Thierry
2019-01-31  8:19       ` Christoffer Dall
2019-01-31  8:56         ` Julien Thierry
2019-01-31  9:27           ` Christoffer Dall
2019-01-31  9:40             ` Julien Thierry
2019-01-31  9:48               ` Christoffer Dall
2019-01-31  9:53               ` Marc Zyngier
2019-01-21 15:33 ` [PATCH v9 02/26] arm64: Remove unused daif related functions/macros Julien Thierry
2019-01-28  9:21   ` Marc Zyngier
2019-01-21 15:33 ` [PATCH v9 03/26] arm64: cpufeature: Set SYSREG_GIC_CPUIF as a boot system feature Julien Thierry
2019-01-28  9:22   ` Marc Zyngier
2019-01-21 15:33 ` [PATCH v9 04/26] arm64: cpufeature: Add cpufeature for IRQ priority masking Julien Thierry
2019-01-28  9:24   ` Marc Zyngier
2019-01-21 15:33 ` [PATCH v9 05/26] arm/arm64: gic-v3: Add PMR and RPR accessors Julien Thierry
2019-01-28  9:25   ` Marc Zyngier
2019-01-21 15:33 ` [PATCH v9 06/26] irqchip/gic-v3: Switch to PMR masking before calling IRQ handler Julien Thierry
2019-01-28  9:30   ` Marc Zyngier
2019-01-21 15:33 ` [PATCH v9 07/26] arm64: ptrace: Provide definitions for PMR values Julien Thierry
2019-01-28  9:37   ` Marc Zyngier
2019-01-21 15:33 ` [PATCH v9 08/26] arm64: Make PMR part of task context Julien Thierry
2019-01-28  9:42   ` Marc Zyngier
2019-01-21 15:33 ` [PATCH v9 09/26] arm64: Unmask PMR before going idle Julien Thierry
2019-01-22 15:23   ` Catalin Marinas
2019-01-22 20:18   ` Ard Biesheuvel
2019-01-23  8:56     ` Julien Thierry
2019-01-23  9:38       ` Ard Biesheuvel
2019-01-28  9:44   ` Marc Zyngier
2019-01-21 15:33 ` [PATCH v9 10/26] arm64: kvm: Unmask PMR before entering guest Julien Thierry
2019-01-28  9:58   ` Marc Zyngier
2019-01-30 12:07   ` Christoffer Dall
2019-01-30 14:58     ` Julien Thierry
2019-01-21 15:33 ` [PATCH v9 11/26] efi: Let architectures decide the flags that should be saved/restored Julien Thierry
2019-01-21 15:42   ` Ard Biesheuvel
2019-01-23  9:04     ` Julien Thierry
2019-01-28 10:00   ` Marc Zyngier
2019-01-21 15:33 ` [PATCH v9 12/26] arm64: irqflags: Use ICC_PMR_EL1 for interrupt masking Julien Thierry
2019-01-21 15:45   ` Ard Biesheuvel
2019-01-21 18:05     ` Julien Thierry
2019-01-22 15:21   ` Catalin Marinas
2019-01-23 10:44     ` Julien Thierry
2019-01-30 11:52       ` Julien Thierry
2019-01-21 15:33 ` [PATCH v9 13/26] arm64: daifflags: Include PMR in daifflags restore operations Julien Thierry
2019-01-28 10:37   ` Marc Zyngier
2019-01-21 15:33 ` [PATCH v9 14/26] arm64: alternative: Allow alternative status checking per cpufeature Julien Thierry
2019-01-28 11:00   ` Marc Zyngier
2019-01-21 15:33 ` [PATCH v9 15/26] arm64: alternative: Apply alternatives early in boot process Julien Thierry
2019-01-28 11:17   ` Marc Zyngier
2019-01-21 15:33 ` [PATCH v9 16/26] irqchip/gic-v3: Factor group0 detection into functions Julien Thierry
2019-01-28 11:19   ` Marc Zyngier
2019-01-21 15:33 ` [PATCH v9 17/26] arm64: Switch to PMR masking when starting CPUs Julien Thierry
2019-01-28 11:21   ` Marc Zyngier
2019-01-21 15:33 ` [PATCH v9 18/26] arm64: gic-v3: Implement arch support for priority masking Julien Thierry
2019-01-28 11:23   ` Marc Zyngier
2019-01-21 15:33 ` [PATCH v9 19/26] irqchip/gic-v3: Detect if GIC can support pseudo-NMIs Julien Thierry
2019-01-28 11:39   ` Marc Zyngier
2019-01-21 15:33 ` [PATCH v9 20/26] irqchip/gic-v3: Handle pseudo-NMIs Julien Thierry
2019-01-28 11:59   ` Marc Zyngier
2019-01-29 11:33     ` Julien Thierry
2019-01-29 12:31       ` Marc Zyngier
2019-01-21 15:33 ` [PATCH v9 21/26] irqchip/gic: Add functions to access irq priorities Julien Thierry
2019-01-28 12:04   ` Marc Zyngier
2019-01-29 11:36     ` Julien Thierry
2019-01-21 15:33 ` [PATCH v9 22/26] irqchip/gic-v3: Allow interrupts to be set as pseudo-NMI Julien Thierry
2019-01-26 10:19   ` liwei (GF)
2019-01-26 10:41     ` Marc Zyngier
2019-01-28  8:57     ` Julien Thierry
2019-01-28 13:59       ` liwei (GF)
2019-01-28 14:49         ` Julien Thierry
2019-01-28 12:08   ` Marc Zyngier
2019-01-21 15:33 ` [PATCH v9 23/26] arm64: Handle serror in NMI context Julien Thierry
2019-01-28 12:26   ` Marc Zyngier
2019-01-21 15:33 ` [PATCH v9 24/26] arm64: Skip preemption when exiting an NMI Julien Thierry
2019-01-28 12:34   ` Marc Zyngier
2019-01-21 15:33 ` [PATCH v9 25/26] arm64: Skip irqflags tracing for NMI in IRQs disabled context Julien Thierry
2019-01-28 12:40   ` Marc Zyngier
2019-01-21 15:33 ` [PATCH v9 26/26] arm64: Enable the support of pseudo-NMIs Julien Thierry
2019-01-28 12:47   ` Marc Zyngier
2019-01-30 13:46     ` Julien Thierry

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=1548084825-8803-2-git-send-email-julien.thierry@arm.com \
    --to=julien.thierry@arm.com \
    --cc=arnd@arndb.de \
    --cc=catalin.marinas@arm.com \
    --cc=christoffer.dall@arm.com \
    --cc=daniel.thompson@linaro.org \
    --cc=james.morse@arm.com \
    --cc=joel@joelfernandes.org \
    --cc=linux-arch@vger.kernel.org \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=marc.zyngier@arm.com \
    --cc=mark.rutland@arm.com \
    --cc=stable@vger.kernel.org \
    --cc=will.deacon@arm.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).