From: Sowjanya Komatineni <skomatineni@nvidia.com>
To: <thierry.reding@gmail.com>, <jonathanh@nvidia.com>,
<talho@nvidia.com>, <skomatineni@nvidia.com>,
<broonie@kernel.org>, <robh+dt@kernel.org>,
<mark.rutland@arm.com>, <kyarlagadda@nvidia.com>
Cc: <ldewangan@nvidia.com>, <linux-tegra@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <linux-spi@vger.kernel.org>,
<devicetree@vger.kernel.org>
Subject: [PATCH V1 17/26] spi: tegra114: add support for interrupt mask
Date: Tue, 26 Mar 2019 22:56:38 -0700 [thread overview]
Message-ID: <1553666207-11414-17-git-send-email-skomatineni@nvidia.com> (raw)
In-Reply-To: <1553666207-11414-1-git-send-email-skomatineni@nvidia.com>
This patch creates tegra_spi_soc_data structure to maintain and implement
SPI HW feature differences between different Tegra chips and also creates
a separate compatible string for T124/T210/T186.
Tegra210 and later has a separate interrupt mask register SPI_INTR_MASK
for enabling or disabling interrupts while Tegra124 and prior uses
interrupt enable bits in SPI_DMA_CTL register.
This patch creates flag has_intr_mask_reg in tegra_spi_soc_data to
identify this and implements accordingly.
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
drivers/spi/spi-tegra114.c | 53 +++++++++++++++++++++++++++++++++++++++++-----
1 file changed, 48 insertions(+), 5 deletions(-)
diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c
index 9b9d4b9e1f3e..68fee474580b 100644
--- a/drivers/spi/spi-tegra114.c
+++ b/drivers/spi/spi-tegra114.c
@@ -149,6 +149,8 @@
#define SPI_TX_FIFO 0x108
#define SPI_RX_FIFO 0x188
+#define SPI_INTR_MASK 0x18c
+#define SPI_INTR_ALL_MASK (0x1fUL << 25)
#define MAX_CHIP_SELECT 4
#define SPI_FIFO_DEPTH 64
#define DATA_DIR_TX (1 << 0)
@@ -161,6 +163,10 @@
#define MAX_HOLD_CYCLES 16
#define SPI_DEFAULT_SPEED 25000000
+struct tegra_spi_soc_data {
+ bool has_intr_mask_reg;
+};
+
struct tegra_spi_data {
struct device *dev;
struct spi_master *master;
@@ -211,6 +217,7 @@ struct tegra_spi_data {
u32 *tx_dma_buf;
dma_addr_t tx_dma_phys;
struct dma_async_tx_descriptor *tx_dma_desc;
+ const struct tegra_spi_soc_data *soc_data;
};
static int tegra_spi_runtime_suspend(struct device *dev);
@@ -554,11 +561,13 @@ static int tegra_spi_start_dma_based_transfer(
dma_burst = 8;
}
- if (tspi->cur_direction & DATA_DIR_TX)
- val |= SPI_IE_TX;
+ if (!tspi->soc_data->has_intr_mask_reg) {
+ if (tspi->cur_direction & DATA_DIR_TX)
+ val |= SPI_IE_TX;
- if (tspi->cur_direction & DATA_DIR_RX)
- val |= SPI_IE_RX;
+ if (tspi->cur_direction & DATA_DIR_RX)
+ val |= SPI_IE_RX;
+ }
tegra_spi_writel(tspi, val, SPI_DMA_CTL);
tspi->dma_control_reg = val;
@@ -848,6 +857,12 @@ static int tegra_spi_setup(struct spi_device *spi)
return ret;
}
+ if (tspi->soc_data->has_intr_mask_reg) {
+ val = tegra_spi_readl(tspi, SPI_INTR_MASK);
+ val &= ~SPI_INTR_ALL_MASK;
+ tegra_spi_writel(tspi, val, SPI_INTR_MASK);
+ }
+
spin_lock_irqsave(&tspi->lock, flags);
val = tspi->def_command1_reg;
if (spi->mode & SPI_CS_HIGH)
@@ -1126,8 +1141,29 @@ static irqreturn_t tegra_spi_isr(int irq, void *context_data)
return IRQ_WAKE_THREAD;
}
+static struct tegra_spi_soc_data tegra114_spi_soc_data = {
+ .has_intr_mask_reg = false,
+};
+
+static struct tegra_spi_soc_data tegra124_spi_soc_data = {
+ .has_intr_mask_reg = false,
+};
+
+static struct tegra_spi_soc_data tegra210_spi_soc_data = {
+ .has_intr_mask_reg = true,
+};
+
static const struct of_device_id tegra_spi_of_match[] = {
- { .compatible = "nvidia,tegra114-spi", },
+ {
+ .compatible = "nvidia,tegra114-spi",
+ .data = &tegra114_spi_soc_data,
+ }, {
+ .compatible = "nvidia,tegra124-spi",
+ .data = &tegra124_spi_soc_data,
+ }, {
+ .compatible = "nvidia,tegra210-spi",
+ .data = &tegra210_spi_soc_data,
+ },
{}
};
MODULE_DEVICE_TABLE(of, tegra_spi_of_match);
@@ -1168,6 +1204,13 @@ static int tegra_spi_probe(struct platform_device *pdev)
tspi->dev = &pdev->dev;
spin_lock_init(&tspi->lock);
+ tspi->soc_data = of_device_get_match_data(&pdev->dev);
+ if (!tspi->soc_data) {
+ dev_err(&pdev->dev, "unsupported tegra\n");
+ ret = -ENODEV;
+ goto exit_free_master;
+ }
+
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
tspi->base = devm_ioremap_resource(&pdev->dev, r);
if (IS_ERR(tspi->base)) {
--
2.7.4
next prev parent reply other threads:[~2019-03-27 5:58 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-27 5:56 [PATCH V1 01/26] spi: tegra114: fix PIO transfer Sowjanya Komatineni
2019-03-27 5:56 ` [PATCH V1 02/26] spi: tegra114: clear packed bit for unpacked mode Sowjanya Komatineni
2019-04-01 8:54 ` Applied "spi: tegra114: clear packed bit for unpacked mode" to the spi tree Mark Brown
2019-03-27 5:56 ` [PATCH V1 03/26] spi: tegra114: fix for unpacked mode transfers Sowjanya Komatineni
2019-04-01 8:54 ` Applied "spi: tegra114: fix for unpacked mode transfers" to the spi tree Mark Brown
2019-03-27 5:56 ` [PATCH V1 04/26] spi: tegra114: use packed mode for 32 bits per word Sowjanya Komatineni
2019-04-01 7:39 ` Mark Brown
2019-04-01 18:38 ` Sowjanya Komatineni
2019-04-01 8:54 ` Applied "spi: tegra114: use packed mode for 32 bits per word" to the spi tree Mark Brown
2019-03-27 5:56 ` [PATCH V1 05/26] spi: tegra114: use unpacked mode for below 4 byte transfers Sowjanya Komatineni
2019-04-01 8:26 ` Mark Brown
2019-03-27 5:56 ` [PATCH V1 06/26] spi: tegra114: terminate dma and reset on transfer timeout Sowjanya Komatineni
2019-04-01 8:54 ` Applied "spi: tegra114: terminate dma and reset on transfer timeout" to the spi tree Mark Brown
2019-03-27 5:56 ` [PATCH V1 07/26] spi: tegra114: flush fifos Sowjanya Komatineni
2019-04-01 8:54 ` Applied "spi: tegra114: flush fifos" to the spi tree Mark Brown
2019-03-27 5:56 ` [PATCH V1 08/26] spi: tegra114: configure dma burst size to fifo trig level Sowjanya Komatineni
2019-03-27 5:56 ` [PATCH V1 09/26] spi: tegra114: dump SPI registers during timeout Sowjanya Komatineni
2019-04-01 7:39 ` Mark Brown
2019-03-27 5:56 ` [PATCH V1 10/26] spi: tegra114: avoid reset call in atomic context Sowjanya Komatineni
2019-03-27 5:56 ` [PATCH V1 11/26] spi: tegra114: reset controller on probe Sowjanya Komatineni
2019-04-01 8:54 ` Applied "spi: tegra114: reset controller on probe" to the spi tree Mark Brown
2019-03-27 5:56 ` [PATCH V1 12/26] spi: tegra114: add SPI_LSB_FIRST support Sowjanya Komatineni
2019-04-01 8:54 ` Applied "spi: tegra114: add SPI_LSB_FIRST support" to the spi tree Mark Brown
2019-03-27 5:56 ` [PATCH V1 13/26] spi: tegra114: add dual mode support Sowjanya Komatineni
2019-03-27 5:56 ` [PATCH V1 14/26] spi: tegra114: add 3 wire transfer " Sowjanya Komatineni
2019-03-27 5:56 ` [PATCH V1 15/26] spi: tegra114: set supported bits_per_word Sowjanya Komatineni
2019-03-27 5:56 ` [PATCH V1 16/26] spi: tegra114: set bus number based on id Sowjanya Komatineni
2019-03-27 5:56 ` Sowjanya Komatineni [this message]
2019-03-27 5:56 ` [PATCH V1 18/26] spi: tegra114: add support for hw based cs Sowjanya Komatineni
2019-04-01 7:48 ` Mark Brown
2019-04-01 18:40 ` Sowjanya Komatineni
2019-03-27 5:56 ` [PATCH V1 19/26] DT bindings: spi: add spi client device properties Sowjanya Komatineni
2019-04-01 7:37 ` Mark Brown
2019-04-01 17:59 ` Sowjanya Komatineni
2019-04-02 4:52 ` Mark Brown
2019-03-27 5:56 ` [PATCH V1 20/26] spi: tegra114: add support for tuning HW CS timing Sowjanya Komatineni
2019-03-27 5:56 ` [PATCH V1 21/26] DT bindings: spi: add tx/rx clock delay SPI client properties Sowjanya Komatineni
2019-03-31 6:42 ` Rob Herring
2019-04-02 20:27 ` Sowjanya Komatineni
2019-03-27 5:56 ` [PATCH V1 22/26] spi: tegra114: add support for tuning clock delay Sowjanya Komatineni
2019-03-27 5:56 ` [PATCH V1 23/26] spi: tegra114: add support for gpio based cs Sowjanya Komatineni
2019-03-27 5:56 ` [PATCH V1 24/26] spi: tegra114: de-assert CS before SPI mode is reset to its default Sowjanya Komatineni
2019-04-01 7:49 ` Mark Brown
2019-04-01 18:07 ` Sowjanya Komatineni
2019-04-02 4:52 ` Mark Brown
2019-03-27 5:56 ` [PATCH V1 25/26] spi: expand mode and mode_bits support Sowjanya Komatineni
2019-03-27 5:56 ` [PATCH V1 26/26] spi: tegra114: add support for LSBYTE_FIRST Sowjanya Komatineni
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