From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 97D36C43219 for ; Tue, 30 Apr 2019 09:46:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 740DE217D4 for ; Tue, 30 Apr 2019 09:46:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727354AbfD3JqJ (ORCPT ); Tue, 30 Apr 2019 05:46:09 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:56534 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726977AbfD3Jp2 (ORCPT ); Tue, 30 Apr 2019 05:45:28 -0400 X-UUID: 56453f2495454ba191e35d7edb3bba18-20190430 X-UUID: 56453f2495454ba191e35d7edb3bba18-20190430 Received: from mtkcas09.mediatek.inc [(172.21.101.178)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 764078573; Tue, 30 Apr 2019 17:45:21 +0800 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs03n1.mediatek.inc (172.21.101.181) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 30 Apr 2019 17:45:20 +0800 Received: from mtkslt205.mediatek.inc (10.21.15.75) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 30 Apr 2019 17:45:20 +0800 From: Henry Chen To: Georgi Djakov , Rob Herring , Matthias Brugger , Viresh Kumar , Stephen Boyd CC: Nicolas Boichat , Fan Chen , James Liao , Weiyi Lu , , , , , Henry Chen Subject: [RFC V2 08/11] dt-bindings: interconnect: add MT8183 interconnect dt-bindings Date: Tue, 30 Apr 2019 16:51:02 +0800 Message-ID: <1556614265-12745-9-git-send-email-henryc.chen@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1556614265-12745-1-git-send-email-henryc.chen@mediatek.com> References: <1556614265-12745-1-git-send-email-henryc.chen@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add interconnect provider dt-bindings for MT8183. Signed-off-by: Henry Chen --- .../bindings/interconnect/mtk,mt8183.txt | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 Documentation/devicetree/bindings/interconnect/mtk,mt8183.txt diff --git a/Documentation/devicetree/bindings/interconnect/mtk,mt8183.txt b/Documentation/devicetree/bindings/interconnect/mtk,mt8183.txt new file mode 100644 index 0000000..1cf1841 --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/mtk,mt8183.txt @@ -0,0 +1,24 @@ +Mediatek MT8183 interconnect binding + +MT8183 interconnect providers support dram bandwidth requirements. The provider +is able to communicate with the DVFSRC and send the dram bandwidth to it. +Provider nodes must reside within an DVFSRC device node. + +Required properties : +- compatible : shall contain only one of the following: + "mediatek,mt8183-emi-icc" +- #interconnect-cells : should contain 1 + +Examples: + +dvfsrc@10012000 { + compatible = "mediatek,mt8183-dvfsrc"; + reg = <0 0x10012000 0 0x1000>; + clocks = <&infracfg CLK_INFRA_DVFSRC>; + clock-names = "dvfsrc"; + ddr_emi: interconnect { + compatible = "mediatek,mt8183-emi-icc"; + #interconnect-cells = <1>; + }; +}; + -- 1.9.1