From: Hector Yuan <hector.yuan@mediatek.com>
To: <linux-mediatek@lists.infradead.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-pm@vger.kernel.org>, Rob Herring <robh+dt@kernel.org>,
Sudeep Holla <sudeep.holla@arm.com>,
"Rafael J. Wysocki" <rjw@rjwysocki.net>,
Viresh Kumar <viresh.kumar@linaro.org>,
Maxime Ripard <mripard@kernel.org>,
Santosh Shilimkar <ssantosh@kernel.org>,
Amit Kucheria <amit.kucheria@linaro.org>,
Stephen Boyd <sboyd@kernel.org>,
Ulf Hansson <ulf.hansson@linaro.org>,
Dave Gerlach <d-gerlach@ti.com>,
Florian Fainelli <f.fainelli@gmail.com>,
Robin Murphy <robin.murphy@arm.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
<devicetree@vger.kernel.org>
Cc: <linux-kernel@vger.kernel.org>, <wsd_upstream@mediatek.com>,
<hector.yuan@mediatek.com>
Subject: [PATCH v8 3/3] dt-bindings: cpufreq: add bindings for MediaTek cpufreq HW
Date: Mon, 26 Oct 2020 16:19:09 +0800 [thread overview]
Message-ID: <1603700349-5922-4-git-send-email-hector.yuan@mediatek.com> (raw)
In-Reply-To: <1603700349-5922-1-git-send-email-hector.yuan@mediatek.com>
From: "Hector.Yuan" <hector.yuan@mediatek.com>
Add devicetree bindings for MediaTek HW driver.
Signed-off-by: Hector.Yuan <hector.yuan@mediatek.com>
---
.../bindings/cpufreq/cpufreq-mediatek-hw.yaml | 113 ++++++++++++++++++++
1 file changed, 113 insertions(+)
create mode 100644 Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml
diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml
new file mode 100644
index 0000000..32d2ad4
--- /dev/null
+++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml
@@ -0,0 +1,113 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/cpufreq/cpufreq-mediatek-hw.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek's CPUFREQ Bindings
+
+maintainers:
+ - Hector Yuan <hector.yuan@mediatek.com>
+
+description:
+ CPUFREQ HW is a hardware engine used by MediaTek
+ SoCs to manage frequency in hardware. It is capable of controlling frequency
+ for multiple clusters.
+
+properties:
+ compatible:
+ const: mediatek,cpufreq-hw
+
+ reg:
+ minItems: 1
+ maxItems: 2
+ description: |
+ Addresses and sizes for the memory of the HW bases in each frequency domain.
+
+required:
+ - compatible
+ - reg
+
+examples:
+ - |
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ enable-method = "psci";
+ mediatek,freq-domain = <&cpufreq_hw 0>;
+ reg = <0x000>;
+ };
+
+ cpu1: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ enable-method = "psci";
+ mediatek,freq-domain = <&cpufreq_hw 0>;
+ reg = <0x100>;
+ };
+
+ cpu2: cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ enable-method = "psci";
+ mediatek,freq-domain = <&cpufreq_hw 0>;
+ reg = <0x200>;
+ };
+
+ cpu3: cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ enable-method = "psci";
+ mediatek,freq-domain = <&cpufreq_hw 0>;
+ reg = <0x300>;
+ };
+
+ cpu4: cpu@400 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ enable-method = "psci";
+ mediatek,freq-domain = <&cpufreq_hw 1>;
+ reg = <0x400>;
+ };
+
+ cpu5: cpu@500 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ enable-method = "psci";
+ mediatek,freq-domain = <&cpufreq_hw 1>;
+ reg = <0x500>;
+ };
+
+ cpu6: cpu@600 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a75";
+ enable-method = "psci";
+ mediatek,freq-domain = <&cpufreq_hw 1>;
+ reg = <0x600>;
+ };
+
+ cpu7: cpu@700 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a75";
+ enable-method = "psci";
+ mediatek,freq-domain = <&cpufreq_hw 1>;
+ reg = <0x700>;
+ };
+ };
+
+ /* ... */
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpufreq_hw: cpufreq@11bc00 {
+ compatible = "mediatek,cpufreq-hw";
+ reg = <0 0x11bc10 0 0x8c>,
+ <0 0x11bca0 0 0x8c>;
+ };
+ };
--
1.7.9.5
prev parent reply other threads:[~2020-10-26 8:19 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-26 8:19 [PATCH v8] cpufreq: mediatek-hw: Add support for Mediatek cpufreq HW driver Hector Yuan
2020-10-26 8:19 ` [PATCH v8 1/3] cpufreq: mediatek-hw: Add support for CPUFREQ HW Hector Yuan
2020-11-19 12:41 ` Lukasz Luba
2020-11-19 13:40 ` Hector Yuan
2020-11-19 15:14 ` Lukasz Luba
2020-10-26 8:19 ` [PATCH v8 2/3] dt-bindings: arm: cpus: Document 'mediatek,freq-domain' property Hector Yuan
2020-10-28 15:08 ` Rob Herring
2020-11-19 15:23 ` Lukasz Luba
2020-11-19 17:13 ` Sudeep Holla
2020-11-20 8:35 ` Lukasz Luba
2020-10-26 8:19 ` Hector Yuan [this message]
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