From: Tiffany Lin <tiffany.lin@mediatek.com>
To: Irui Wang <irui.wang@mediatek.com>
Cc: Alexandre Courbot <acourbot@chromium.org>,
Hans Verkuil <hverkuil-cisco@xs4all.nl>,
Andrew-CT Chen <andrew-ct.chen@mediatek.com>,
Mauro Carvalho Chehab <mchehab@kernel.org>,
Rob Herring <robh+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
"Tomasz Figa" <tfiga@google.com>,
Hsin-Yi Wang <hsinyi@chromium.org>,
Maoguang Meng <maoguang.meng@mediatek.com>,
Longfei Wang <longfei.wang@mediatek.com>,
Yunfei Dong <yunfei.dong@mediatek.com>,
<linux-media@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<srv_heupstream@mediatek.com>,
<linux-mediatek@lists.infradead.org>
Subject: Re: [PATCH 2/3] arm64: dts: mt8173: Separating mtk-vcodec-enc device node
Date: Tue, 26 Jan 2021 16:43:59 +0800 [thread overview]
Message-ID: <1611650639.20687.2.camel@mtksdaap41> (raw)
In-Reply-To: <20210121061804.26423-2-irui.wang@mediatek.com>
On Thu, 2021-01-21 at 14:18 +0800, Irui Wang wrote:
> There are two separate hardware encoder blocks inside MT8173.
> Split the current mtk-vcodec-enc node to match the hardware architecture.
>
> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
> Signed-off-by: Maoguang Meng <maoguang.meng@mediatek.com>
> Signed-off-by: Irui Wang <irui.wang@mediatek.com>
>
Acked-by: Tiffany Lin <tiffany.lin@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8173.dtsi | 60 ++++++++++++------------
> 1 file changed, 31 insertions(+), 29 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> index 7fa870e4386a..d667b296c512 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> @@ -1459,13 +1459,10 @@
> };
>
> vcodec_enc: vcodec@18002000 {
> - compatible = "mediatek,mt8173-vcodec-enc";
> - reg = <0 0x18002000 0 0x1000>, /* VENC_SYS */
> - <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */
> - interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>,
> - <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
> - mediatek,larb = <&larb3>,
> - <&larb5>;
> + compatible = "mediatek,mt8173-vcodec-avc-enc";
> + reg = <0 0x18002000 0 0x1000>; /* VENC_SYS */
> + interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
> + mediatek,larb = <&larb3>;
> iommus = <&iommu M4U_PORT_VENC_RCPU>,
> <&iommu M4U_PORT_VENC_REC>,
> <&iommu M4U_PORT_VENC_BSDMA>,
> @@ -1476,29 +1473,12 @@
> <&iommu M4U_PORT_VENC_REF_LUMA>,
> <&iommu M4U_PORT_VENC_REF_CHROMA>,
> <&iommu M4U_PORT_VENC_NBM_RDMA>,
> - <&iommu M4U_PORT_VENC_NBM_WDMA>,
> - <&iommu M4U_PORT_VENC_RCPU_SET2>,
> - <&iommu M4U_PORT_VENC_REC_FRM_SET2>,
> - <&iommu M4U_PORT_VENC_BSDMA_SET2>,
> - <&iommu M4U_PORT_VENC_SV_COMA_SET2>,
> - <&iommu M4U_PORT_VENC_RD_COMA_SET2>,
> - <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>,
> - <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
> - <&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
> - <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
> + <&iommu M4U_PORT_VENC_NBM_WDMA>;
> mediatek,vpu = <&vpu>;
> - clocks = <&topckgen CLK_TOP_VENCPLL_D2>,
> - <&topckgen CLK_TOP_VENC_SEL>,
> - <&topckgen CLK_TOP_UNIVPLL1_D2>,
> - <&topckgen CLK_TOP_VENC_LT_SEL>;
> - clock-names = "venc_sel_src",
> - "venc_sel",
> - "venc_lt_sel_src",
> - "venc_lt_sel";
> - assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>,
> - <&topckgen CLK_TOP_VENC_LT_SEL>;
> - assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>,
> - <&topckgen CLK_TOP_VCODECPLL_370P5>;
> + clocks = <&topckgen CLK_TOP_VENC_SEL>;
> + clock-names = "venc_sel";
> + assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
> + assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>;
> };
>
> jpegdec: jpegdec@18004000 {
> @@ -1530,5 +1510,27 @@
> <&vencltsys CLK_VENCLT_CKE0>;
> clock-names = "apb", "smi";
> };
> +
> + vcodec_enc_lt: vcodec@19002000 {
> + compatible = "mediatek,mt8173-vcodec-vp8-enc";
> + reg = <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */
> + interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
> + iommus = <&iommu M4U_PORT_VENC_RCPU_SET2>,
> + <&iommu M4U_PORT_VENC_REC_FRM_SET2>,
> + <&iommu M4U_PORT_VENC_BSDMA_SET2>,
> + <&iommu M4U_PORT_VENC_SV_COMA_SET2>,
> + <&iommu M4U_PORT_VENC_RD_COMA_SET2>,
> + <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>,
> + <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
> + <&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
> + <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
> + mediatek,larb = <&larb5>;
> + mediatek,vpu = <&vpu>;
> + clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
> + clock-names = "venc_lt_sel";
> + assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
> + assigned-clock-parents =
> + <&topckgen CLK_TOP_VCODECPLL_370P5>;
> + };
> };
> };
next prev parent reply other threads:[~2021-01-26 17:54 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-21 6:18 [PATCH 1/3] dt-bindings: media: mtk-vcodec: Separating mtk vcodec encoder node Irui Wang
2021-01-21 6:18 ` [PATCH 2/3] arm64: dts: mt8173: Separating mtk-vcodec-enc device node Irui Wang
2021-01-26 8:43 ` Tiffany Lin [this message]
2021-01-21 6:18 ` [PATCH 3/3] media: mtk-vcodec: Separating mtk encoder driver Irui Wang
2021-01-26 8:44 ` Tiffany Lin
2021-02-03 10:44 ` Alexandre Courbot
2021-02-20 6:55 ` Irui Wang
2021-02-22 13:03 ` Alexandre Courbot
2021-01-26 8:42 ` [PATCH 1/3] dt-bindings: media: mtk-vcodec: Separating mtk vcodec encoder node Tiffany Lin
2021-02-03 10:44 ` Alexandre Courbot
2021-02-20 6:26 ` Irui Wang
2021-02-09 15:53 ` Rob Herring
2021-02-20 6:33 ` Irui Wang
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