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From: Jianjun Wang <jianjun.wang@mediatek.com>
To: "Krzysztof Wilczyński" <kw@linux.com>
Cc: Bjorn Helgaas <helgaas@kernel.org>,
	Rob Herring <robh+dt@kernel.org>, <maz@kernel.org>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Ryder Lee <ryder.lee@mediatek.com>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	"Matthias Brugger" <matthias.bgg@gmail.com>,
	<linux-pci@vger.kernel.org>, <linux-mediatek@lists.infradead.org>,
	<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	"Sj Huang" <sj.huang@mediatek.com>, <youlin.pei@mediatek.com>,
	<chuanjia.liu@mediatek.com>, <qizhong.cheng@mediatek.com>,
	<sin_jieyang@mediatek.com>, <drinkcat@chromium.org>,
	<Rex-BC.Chen@mediatek.com>, <anson.chuang@mediatek.com>
Subject: Re: [v8,3/7] PCI: mediatek-gen3: Add MediaTek Gen3 driver for MT8192
Date: Thu, 25 Feb 2021 11:07:27 +0800	[thread overview]
Message-ID: <1614222447.25750.6.camel@mhfsdcap03> (raw)
In-Reply-To: <YDZWUGcKet/lNWlF@rocinante>

Hi Krzysztof,

Thanks for your review, I will fix these at next version.

Thanks.

On Wed, 2021-02-24 at 14:36 +0100, Krzysztof Wilczyński wrote:
> Hi Jianjun,
> 
> Thank you for all the work here!
> 
> [...]
> > + * struct mtk_pcie_port - PCIe port information
> > + * @dev: pointer to PCIe device
> > + * @base: IO mapped register base
> > + * @reg_base: Physical register base
> > + * @mac_reset: mac reset control
> > + * @phy_reset: phy reset control
> > + * @phy: PHY controller block
> > + * @clks: PCIe clocks
> > + * @num_clks: PCIe clocks count for this port
> 
> It would be "MAC" and "PHY" in the above.
> 
> [...]
> > + * mtk_pcie_config_tlp_header
> > + * @bus: PCI bus to query
> > + * @devfn: device/function number
> > + * @where: offset in config space
> > + * @size: data size in TLP header
> > + *
> > + * Set byte enable field and device information in configuration TLP header.
> 
> The kernel-doc above might be missing brief function description.  See
> the following for more concrete example:
> 
>   https://www.kernel.org/doc/html/latest/doc-guide/kernel-doc.html#function-documentation
> 
> [...]
> > +static int mtk_pcie_set_trans_table(struct mtk_pcie_port *port,
> > +				    resource_size_t cpu_addr,
> > +				    resource_size_t pci_addr,
> > +				    resource_size_t size,
> > +				    unsigned long type, int num)
> > +{
> > +	void __iomem *table;
> > +	u32 val;
> > +
> > +	if (num >= PCIE_MAX_TRANS_TABLES) {
> > +		dev_err(port->dev, "not enough translate table[%d] for addr: %#llx, limited to [%d]\n",
> 
> The wording of this error message is a little confusing.
> 
> > +			num, (unsigned long long) cpu_addr,
> 
> No space between the bracket and the variable name.
> 
> [...]
> > +	err = phy_init(port->phy);
> > +	if (err) {
> > +		dev_err(dev, "failed to initialize PCIe phy\n");
> > +		goto err_phy_init;
> > +	}
> > +
> > +	err = phy_power_on(port->phy);
> > +	if (err) {
> > +		dev_err(dev, "failed to power on PCIe phy\n");
> > +		goto err_phy_on;
> > +	}
> [...]
> 
> It would be "PHY" in the error messages above.
> 
> [...]
> > +	if (err) {
> > +		dev_err(dev, "clock init failed\n");
> > +		goto err_clk_init;
> > +	}
> [...]
> 
> A nitpick, so feel free to ignore it, of course.  What about "failed to
> initialize clock" to keep the style consistent.
> 
> [...]
> > +	err = mtk_pcie_startup_port(port);
> > +	if (err) {
> > +		dev_err(dev, "PCIe startup failed\n");
> [...]
> 
> Also a nitpick.  What about "failed to bring PCIe link up"?
> 
> Krzysztof


  reply	other threads:[~2021-02-25  3:09 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-02-24  6:11 [v8,0/7] PCI: mediatek: Add new generation controller support Jianjun Wang
2021-02-24  6:11 ` [v8,1/7] dt-bindings: PCI: mediatek-gen3: Add YAML schema Jianjun Wang
2021-03-06 20:09   ` Rob Herring
2021-02-24  6:11 ` [v8,2/7] PCI: Export pci_pio_to_address() for module use Jianjun Wang
2021-02-24  6:11 ` [v8,3/7] PCI: mediatek-gen3: Add MediaTek Gen3 driver for MT8192 Jianjun Wang
2021-02-24 13:36   ` Krzysztof Wilczyński
2021-02-25  3:07     ` Jianjun Wang [this message]
2021-03-11 12:38   ` Pali Rohár
2021-03-13  7:43     ` Jianjun Wang
2021-03-18  0:02       ` Pali Rohár
2021-03-18  5:48         ` Jianjun Wang
2021-03-19 18:53           ` Pali Rohár
2021-03-23  1:31             ` Jianjun Wang
2021-03-23 14:51               ` Pali Rohár
2021-03-29 22:58           ` Pali Rohár
2021-02-24  6:11 ` [v8,4/7] PCI: mediatek-gen3: Add INTx support Jianjun Wang
2021-02-24 14:24   ` Krzysztof Wilczyński
2021-02-25  3:10     ` Jianjun Wang
2021-03-09 11:10   ` Marc Zyngier
2021-03-10  3:05     ` Jianjun Wang
2021-02-24  6:11 ` [v8,5/7] PCI: mediatek-gen3: Add MSI support Jianjun Wang
2021-02-24 14:31   ` Krzysztof Wilczyński
2021-02-25  3:09     ` Jianjun Wang
2021-03-09 11:23   ` Marc Zyngier
2021-03-10  6:48     ` Jianjun Wang
     [not found]       ` <87a6rbxs4w.wl-maz@kernel.org>
2021-03-11  9:47         ` Jianjun Wang
2021-03-11  0:05   ` Pali Rohár
2021-03-11  8:19     ` Marc Zyngier
2021-03-11  9:50       ` Jianjun Wang
2021-02-24  6:11 ` [v8,6/7] PCI: mediatek-gen3: Add system PM support Jianjun Wang
2021-02-24 14:10   ` Krzysztof Wilczyński
2021-02-25  3:34     ` Jianjun Wang
2021-02-25 22:00       ` Krzysztof Wilczyński
2021-02-26 10:06         ` Jianjun Wang
2021-02-24  6:11 ` [v8,7/7] MAINTAINERS: Add Jianjun Wang as MediaTek PCI co-maintainer Jianjun Wang

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