From: Stephen Boyd <sboyd@kernel.org>
To: Dario Binacchi <dariobin@libero.it>, linux-clk@vger.kernel.org
Cc: Dario Binacchi <dariobin@libero.it>,
Alexandre Torgue <alexandre.torgue@foss.st.com>,
Gabriel Fernandez <gabriel.fernandez@st.com>,
Maxime Coquelin <mcoquelin.stm32@gmail.com>,
Michael Turquette <mturquette@baylibre.com>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org,
linux-stm32@st-md-mailman.stormreply.com
Subject: Re: [RESEND PATCH v4] clk: stm32f4: fix post divisor setup for I2S/SAI PLLs
Date: Mon, 26 Jul 2021 17:22:49 -0700 [thread overview]
Message-ID: <162734536950.2368309.11504276867614624593@swboyd.mtv.corp.google.com> (raw)
In-Reply-To: <20210725160725.10788-1-dariobin@libero.it>
Quoting Dario Binacchi (2021-07-25 09:07:25)
> Enabling the framebuffer leads to a system hang. Running, as a debug
> hack, the store_pan() function in drivers/video/fbdev/core/fbsysfs.c
> without taking the console_lock, allows to see the crash backtrace on
> the serial line.
>
> ~ # echo 0 0 > /sys/class/graphics/fb0/pan
>
> [ 9.719414] Unhandled exception: IPSR = 00000005 LR = fffffff1
> [ 9.726937] CPU: 0 PID: 49 Comm: sh Not tainted 5.13.0-rc5 #9
> [ 9.733008] Hardware name: STM32 (Device Tree Support)
> [ 9.738296] PC is at clk_gate_is_enabled+0x0/0x28
> [ 9.743426] LR is at stm32f4_pll_div_set_rate+0xf/0x38
> [ 9.748857] pc : [<0011e4be>] lr : [<0011f9e3>] psr: 0100000b
> [ 9.755373] sp : 00bc7be0 ip : 00000000 fp : 001f3ac4
> [ 9.760812] r10: 002610d0 r9 : 01efe920 r8 : 00540560
> [ 9.766269] r7 : 02e7ddb0 r6 : 0173eed8 r5 : 00000000 r4 : 004027c0
> [ 9.773081] r3 : 0011e4bf r2 : 02e7ddb0 r1 : 0173eed8 r0 : 1d3267b8
> [ 9.779911] xPSR: 0100000b
> [ 9.782719] CPU: 0 PID: 49 Comm: sh Not tainted 5.13.0-rc5 #9
> [ 9.788791] Hardware name: STM32 (Device Tree Support)
> [ 9.794120] [<0000afa1>] (unwind_backtrace) from [<0000a33f>] (show_stack+0xb/0xc)
> [ 9.802421] [<0000a33f>] (show_stack) from [<0000a8df>] (__invalid_entry+0x4b/0x4c)
>
> The `pll_num' field in the post_div_data configuration contained a wrong
> value which also referenced an uninitialized hardware clock when
> clk_register_pll_div() was called.
>
> Fixes: 517633ef630e ("clk: stm32f4: Add post divisor for I2S & SAI PLLs")
> Signed-off-by: Dario Binacchi <dariobin@libero.it>
> Reviewed-by: Gabriel Fernandez <gabriel.fernandez@st.com>
>
> ---
Applied to clk-fixes
next prev parent reply other threads:[~2021-07-27 0:22 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-25 16:07 [RESEND PATCH v4] clk: stm32f4: fix post divisor setup for I2S/SAI PLLs Dario Binacchi
2021-07-27 0:22 ` Stephen Boyd [this message]
2021-07-28 10:03 ` Dillon Hua
2021-07-29 10:03 ` Dario Binacchi
2021-07-30 19:47 ` Stephen Boyd
2021-07-30 21:22 ` Dario Binacchi
2021-08-01 14:56 ` Dillon Hua
2021-08-01 19:37 ` Dario Binacchi
2021-08-02 22:09 ` Stephen Boyd
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