From: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
To: "Stephen Boyd" <sboyd@kernel.org>,
"Rob Herring" <robh+dt@kernel.org>,
"Manivannan Sadhasivam" <manivannan.sadhasivam@linaro.org>,
"Andreas Färber" <afaerber@suse.de>,
"Michael Turquette" <mturquette@baylibre.com>,
"Edgar Bernardi Righi" <edgar.righi@lsitec.org.br>
Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-actions@lists.infradead.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org
Subject: [PATCH v3 2/6] clk: actions: Fix SD clocks factor table on Owl S500 SoC
Date: Thu, 10 Jun 2021 23:05:22 +0300 [thread overview]
Message-ID: <196c948d708a22b8198c95f064a0f6b6820f9980.1623354574.git.cristian.ciocaltea@gmail.com> (raw)
In-Reply-To: <cover.1623354574.git.cristian.ciocaltea@gmail.com>
Drop the unsupported entries in the factor table used for the SD[0-2]
clocks definitions on the Actions Semi Owl S500 SoC.
Fixes: ed6b4795ece4 ("clk: actions: Add clock driver for S500 SoC")
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
Changes in v3:
- Added Reviewed-by tag from Mani
Changes in v2:
- Re-added entry "{ 24, 1, 25 }" to sd_factor_table, according to the
datasheet (V1.8+), this is a valid divider
drivers/clk/actions/owl-s500.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/actions/owl-s500.c b/drivers/clk/actions/owl-s500.c
index 75b7186185b0..42abdf964044 100644
--- a/drivers/clk/actions/owl-s500.c
+++ b/drivers/clk/actions/owl-s500.c
@@ -127,8 +127,7 @@ static struct clk_factor_table sd_factor_table[] = {
{ 12, 1, 13 }, { 13, 1, 14 }, { 14, 1, 15 }, { 15, 1, 16 },
{ 16, 1, 17 }, { 17, 1, 18 }, { 18, 1, 19 }, { 19, 1, 20 },
{ 20, 1, 21 }, { 21, 1, 22 }, { 22, 1, 23 }, { 23, 1, 24 },
- { 24, 1, 25 }, { 25, 1, 26 }, { 26, 1, 27 }, { 27, 1, 28 },
- { 28, 1, 29 }, { 29, 1, 30 }, { 30, 1, 31 }, { 31, 1, 32 },
+ { 24, 1, 25 },
/* bit8: /128 */
{ 256, 1, 1 * 128 }, { 257, 1, 2 * 128 }, { 258, 1, 3 * 128 }, { 259, 1, 4 * 128 },
@@ -137,8 +136,7 @@ static struct clk_factor_table sd_factor_table[] = {
{ 268, 1, 13 * 128 }, { 269, 1, 14 * 128 }, { 270, 1, 15 * 128 }, { 271, 1, 16 * 128 },
{ 272, 1, 17 * 128 }, { 273, 1, 18 * 128 }, { 274, 1, 19 * 128 }, { 275, 1, 20 * 128 },
{ 276, 1, 21 * 128 }, { 277, 1, 22 * 128 }, { 278, 1, 23 * 128 }, { 279, 1, 24 * 128 },
- { 280, 1, 25 * 128 }, { 281, 1, 26 * 128 }, { 282, 1, 27 * 128 }, { 283, 1, 28 * 128 },
- { 284, 1, 29 * 128 }, { 285, 1, 30 * 128 }, { 286, 1, 31 * 128 }, { 287, 1, 32 * 128 },
+ { 280, 1, 25 * 128 },
{ 0, 0, 0 },
};
--
2.32.0
next prev parent reply other threads:[~2021-06-10 20:06 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-10 20:05 [PATCH v3 0/6] Improve clock support for Actions S500 SoC Cristian Ciocaltea
2021-06-10 20:05 ` [PATCH v3 1/6] clk: actions: Fix UART clock dividers on Owl " Cristian Ciocaltea
2021-06-28 1:46 ` Stephen Boyd
2021-06-10 20:05 ` Cristian Ciocaltea [this message]
2021-06-28 1:47 ` [PATCH v3 2/6] clk: actions: Fix SD clocks factor table " Stephen Boyd
2021-06-10 20:05 ` [PATCH v3 3/6] clk: actions: Fix bisp_factor_table based clocks " Cristian Ciocaltea
2021-06-28 1:47 ` Stephen Boyd
2021-06-10 20:05 ` [PATCH v3 4/6] clk: actions: Fix AHPPREDIV-H-AHB clock chain " Cristian Ciocaltea
2021-06-11 4:11 ` Manivannan Sadhasivam
2021-06-28 1:47 ` Stephen Boyd
2021-06-10 20:05 ` [PATCH v3 5/6] dt-bindings: clock: Add NIC and ETHERNET bindings for Actions " Cristian Ciocaltea
2021-06-28 1:47 ` Stephen Boyd
2021-06-10 20:05 ` [PATCH v3 6/6] clk: actions: Add NIC and ETHERNET clock support " Cristian Ciocaltea
2021-06-28 1:47 ` Stephen Boyd
2021-06-16 16:06 ` [PATCH v3 0/6] Improve " Cristian Ciocaltea
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