From: "David S. Miller" <davem@redhat.com>
To: axboe@suse.de
Cc: linux-kernel@vger.kernel.org, andrea@suse.de
Subject: Re: [patch] zero-bounce highmem I/O
Date: Thu, 16 Aug 2001 06:08:42 -0700 (PDT) [thread overview]
Message-ID: <20010816.060842.99454999.davem@redhat.com> (raw)
In-Reply-To: <20010816145636.B4352@suse.de>
In-Reply-To: <20010816140317.Y4352@suse.de> <20010816.052727.68039859.davem@redhat.com> <20010816145636.B4352@suse.de>
From: Jens Axboe <axboe@suse.de>
Date: Thu, 16 Aug 2001 14:56:36 +0200
On Thu, Aug 16 2001, David S. Miller wrote:
> Enough babbling on my part, I'll have a look at your bounce patch
> later today. :-)
Wait for the next version, I'll clean up the PCI DMA bounce value
stuff first and post a new version.
Ok. I was thinking about the 4GB issue and we could describe it
simply using one platform macro define that could be boolean tested in
both your new block stuff and a fixed up version of the networking's
current ugly HIGHMEM tests.
/* PCI address are equivalent to memory physical addresses.
* As a consequence, the lower 4GB of main memory may be
* addressable using PCI single-address cycles. The rest of
* memory requires the use of dual-address cycles.
*
* If this is false, the kernel assumes that some hardware
* translation mechanism exists to allow all of physical
* memory to be accessed using single-address cycles.
*/
#define PCI_DMA_PHYS_IS_BUS (1)
So you'd get things like:
if (PCI_DMA_PHYS_IS_BUS) {
/* We might need to bounce this. */
if (! dev_dma_in_range(dev, address + len))
address = make_bounce_buffer(dev, address, len);
} else {
/* All physical memory is legal for DMA so there
* is nothing to check.
*/
}
or whatever. You get the idea.
This is really interesting because it means things like the following.
A device which is only capable of 32-bit PCI addressing can still just
use the pci_map_{single,sg}() interfaces yet DMA to all of system
memory. The block and networking layers will never try to bounce stuff.
Basically, this is what happens today with non-CONFIG_HIGHMEM
64-bit platforms, with a particular cost for the cases where
translation is done via bounce buffers (notably ia64).
What do you think?
Later,
David S. Miller
davem@redhat.com
next prev parent reply other threads:[~2001-08-16 13:08 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2001-08-15 7:50 [patch] zero-bounce highmem I/O Jens Axboe
2001-08-15 9:11 ` David S. Miller
2001-08-15 9:17 ` Jens Axboe
2001-08-15 9:26 ` Jens Axboe
2001-08-15 10:22 ` David S. Miller
2001-08-15 11:13 ` Jens Axboe
2001-08-15 11:47 ` David S. Miller
2001-08-15 12:07 ` Jens Axboe
2001-08-15 12:35 ` David S. Miller
2001-08-15 13:10 ` Jens Axboe
2001-08-15 14:25 ` David S. Miller
2001-08-16 11:51 ` Jens Axboe
2001-08-16 11:56 ` David S. Miller
2001-08-16 12:03 ` Jens Axboe
2001-08-16 12:14 ` Gerd Knorr
2001-08-16 12:27 ` David S. Miller
2001-08-16 12:48 ` Jens Axboe
2001-08-16 12:56 ` Jens Axboe
2001-08-16 13:08 ` David S. Miller [this message]
2001-08-16 12:34 ` David S. Miller
2001-08-16 13:35 ` Gerd Knorr
2001-08-16 14:15 ` David S. Miller
2001-08-16 12:28 ` kill alt_address (Re: [patch] zero-bounce highmem I/O) David S. Miller
2001-08-15 14:02 ` [patch] zero-bounce highmem I/O David S. Miller
2001-08-16 5:52 ` Jens Axboe
2001-08-15 19:20 ` Gérard Roudier
2001-08-16 8:12 ` David S. Miller
[not found] <no.id>
2001-08-16 14:56 ` Alan Cox
2001-08-17 10:18 ` Gerd Knorr
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