From: "David S. Miller" <davem@redhat.com>
To: davidm@hpl.hp.com
Cc: davidm@napali.hpl.hp.com, scott.feldman@intel.com,
linux-kernel@vger.kernel.org, netdev@oss.sgi.com
Subject: Re: [patch] e1000 TSO parameter
Date: Tue, 15 Jul 2003 23:30:34 -0700 [thread overview]
Message-ID: <20030715233034.31bf0709.davem@redhat.com> (raw)
In-Reply-To: <16148.61840.663255.863176@napali.hpl.hp.com>
On Tue, 15 Jul 2003 23:32:48 -0700
David Mosberger <davidm@napali.hpl.hp.com> wrote:
> DaveM> No, I mean "bypass L2 cache on miss" for stores. Don't tell
> DaveM> me IA64 doesn't have that? 8) I certainly didn't mean "always
> DaveM> bypass L2 cache" for stores :-)
>
> What I'm saying is that I almost always want copy_user() to put the
> destination data in the cache, even if it isn't cached yet.
No you don't :-)
If you miss, you do a bypass to main memory. Then when the
app asks for the data (if it even does at all, consider that)
it get's a clean copy in it's L2 cache.
Overall it's more efficient this way.
> Many copy_user() calls are for for data structures that
> easily fit in the cache and the data is usually used quickly afterwards.
Absolutely correct. We can't use the cache bypass-on-miss stores on
sparc64 unless the copy is at least a couple of cachelines in size.
It all works out, don't worry :-)
next prev parent reply other threads:[~2003-07-16 6:26 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2003-07-15 4:42 [patch] e1000 TSO parameter Feldman, Scott
2003-07-15 4:45 ` David S. Miller
2003-07-15 4:57 ` David Mosberger
2003-07-15 5:31 ` David Mosberger
2003-07-15 5:38 ` David S. Miller
2003-07-15 23:01 ` David Mosberger
2003-07-16 1:39 ` David S. Miller
2003-07-16 6:32 ` David Mosberger
2003-07-16 6:30 ` David S. Miller [this message]
2003-07-29 6:53 ` Anton Blanchard
2003-07-15 5:11 Feldman, Scott
2003-07-16 0:27 Feldman, Scott
2003-07-16 0:41 ` David Mosberger
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