From: Rob Herring <robh@kernel.org>
To: Rich Felker <dalias@libc.org>
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-sh@vger.kernel.org,
Ian Campbell <ijc+devicetree@hellion.org.uk>,
Kumar Gala <galak@codeaurora.org>,
Mark Rutland <mark.rutland@arm.com>,
Pawel Moll <pawel.moll@arm.com>
Subject: Re: [PATCH v2 02/12] of: add J-Core cpu bindings
Date: Mon, 23 May 2016 15:48:46 -0500 [thread overview]
Message-ID: <20160523204846.GA16081@rob-hp-laptop> (raw)
In-Reply-To: <f3c89e4834665790ff13478c571cc9aaa9de5559.1463708766.git.dalias@libc.org>
On Fri, May 20, 2016 at 02:53:03AM +0000, Rich Felker wrote:
> Signed-off-by: Rich Felker <dalias@libc.org>
> ---
> Documentation/devicetree/bindings/jcore/cpus.txt | 91 ++++++++++++++++++++++++
> 1 file changed, 91 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/jcore/cpus.txt
>
> diff --git a/Documentation/devicetree/bindings/jcore/cpus.txt b/Documentation/devicetree/bindings/jcore/cpus.txt
> new file mode 100644
> index 0000000..00ef112
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/jcore/cpus.txt
> @@ -0,0 +1,91 @@
> +===================
> +J-Core cpu bindings
> +===================
> +
> +The J-Core processors are open source CPU cores that can be built as FPGA
> +soft cores or ASICs. The device tree is also responsible for describing the
> +cache controls and, for SMP configurations, all details of the SMP method,
> +as documented below.
> +
> +
> +---------------------
> +Top-level "cpus" node
> +---------------------
> +
> +Required properties:
> +
> +- #address-cells: Must be 1.
> +
> +- #size-cells: Must be 0.
> +
> +Optional properties:
> +
> +- enable-method: Required only for SMP systems. If present, must be
> + "jcore,spin-table".
> +
> +
> +--------------------
> +Individual cpu nodes
> +--------------------
> +
> +Required properties:
> +
> +- device_type: Must be "cpu".
> +
> +- compatible: Must be "jcore,j2".
Okay to have this, but you should have compatible strings for specific
core implementations. AIUI, J2 is just the ISA.
> +
> +- reg: Must be 0 on uniprocessor systems, or the sequential, zero-based
> + hardware cpu id on SMP systems.
> +
> +Optional properties:
> +
> +- clock-frequency: Clock frequency of the cpu in Hz.
> +
> +- cpu-release-addr: Necessary only for secondary processors on SMP systems
> + using the "jcore,spin-table" enable method. If present, must consist of
> + two cells containing physical addresses. The first cell contains an
> + address which, when written, unblocks the secondary cpu. The second cell
> + contains an address from which the cpu will read its initial program
> + counter when unblocked.
> +
> +
> +---------------------
> +Cache controller node
> +---------------------
> +
> +Required properties:
> +
> +- compatible: Must be "jcore,cache".
That's pretty generic...
> +
> +- reg: A memory range for the cache controller registers.
And standard cache properties? Are size, sets, ways, line size, etc.
discoverable?
> +
> +
> +--------
> +IPI node
> +--------
> +
> +Device trees for SMP systems must have an IPI node representing the mechanism
> +used for inter-processor interrupt generation.
> +
> +Required properties:
> +
> +- compatible: Must be "jcore,ipi-controller".
Again, seems pretty generic.
> +
> +- reg: A memory range used to IPI generation.
> +
> +- interrupts: An irq on which IPI will be received.
> +
> +
> +----------
> +CPUID node
> +----------
> +
> +Device trees for SMP systems must have a CPUID node representing the mechanism
> +used to identify the current processor on which execution is taking place.
> +
> +Required properties:
> +
> +- compatible: Must be "jcore,cpuid-mmio".
> +
> +- reg: A memory range containing a single 32-bit mmio register which produces
> + the current cpu id when read.
This id matches the reg value in cpu node, right? If not, it should.
Rob
next prev parent reply other threads:[~2016-05-23 20:48 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-05-20 2:53 [PATCH v2 00/12] J-core J2 cpu and SoC peripherals support Rich Felker
2016-05-20 2:53 ` [PATCH v2 02/12] of: add J-Core cpu bindings Rich Felker
2016-05-23 20:48 ` Rob Herring [this message]
2016-05-23 21:03 ` Rich Felker
2016-05-23 23:29 ` Rob Herring
2016-05-24 2:39 ` Rich Felker
2016-05-24 21:30 ` Rob Landley
2016-05-25 1:13 ` Rob Herring
2016-05-25 2:33 ` Rich Felker
2016-05-25 13:13 ` Rob Herring
2016-05-20 2:53 ` [PATCH v2 01/12] of: add vendor prefix for J-Core Rich Felker
2016-05-23 20:49 ` Rob Herring
2016-05-20 2:53 ` [PATCH v2 08/12] irqchip: add J-Core AIC driver Rich Felker
2016-05-20 8:08 ` Geert Uytterhoeven
2016-05-20 8:15 ` Marc Zyngier
2016-05-25 4:29 ` Rich Felker
2016-05-20 2:53 ` [PATCH v2 03/12] of: add J-Core interrupt controller bindings Rich Felker
2016-05-20 8:04 ` Geert Uytterhoeven
2016-05-20 22:34 ` Rich Felker
2016-05-21 18:07 ` Geert Uytterhoeven
2016-05-21 19:17 ` Rich Felker
2016-05-23 20:53 ` Rob Herring
2016-05-23 21:13 ` Rich Felker
2016-05-24 8:09 ` Marc Zyngier
2016-05-25 2:25 ` Rich Felker
2016-05-20 2:53 ` [PATCH v2 06/12] sh: add support for J-Core J2 processor Rich Felker
2016-05-20 2:53 ` [PATCH v2 11/12] sh: add defconfig for J-Core J2 Rich Felker
2016-05-20 2:53 ` [PATCH v2 09/12] clocksource: add J-Core PIT/RTC driver Rich Felker
2016-05-20 14:01 ` Daniel Lezcano
2016-05-21 3:15 ` Rich Felker
2016-05-21 15:55 ` Rob Landley
2016-05-23 20:32 ` Daniel Lezcano
2016-05-24 2:25 ` Rich Felker
2016-05-20 2:53 ` [PATCH v2 04/12] of: add J-Core timer bindings Rich Felker
2016-05-20 8:03 ` Geert Uytterhoeven
2016-05-20 2:53 ` [PATCH v2 12/12] sh: add device tree source for J2 FPGA on Mimas v2 board Rich Felker
2016-05-20 8:17 ` Geert Uytterhoeven
2016-05-20 22:42 ` Rich Felker
2016-05-20 2:53 ` [PATCH v2 10/12] spi: add driver for J-Core SPI controller Rich Felker
2016-05-20 8:15 ` Geert Uytterhoeven
2016-05-20 22:50 ` Rich Felker
2016-05-20 10:23 ` Mark Brown
2016-05-20 23:24 ` Rich Felker
2016-05-23 15:30 ` Mark Brown
2016-05-23 20:29 ` Rich Felker
2016-05-23 22:11 ` Mark Brown
2016-05-20 2:53 ` [PATCH v2 07/12] sh: add AT_HWCAP flag for J-Core cas.l instruction Rich Felker
2016-05-20 2:53 ` [PATCH v2 05/12] of: add J-Core SPI master bindings Rich Felker
2016-05-20 8:05 ` Geert Uytterhoeven
2016-05-23 21:00 ` Rob Herring
2016-05-23 21:06 ` Rich Felker
2016-05-23 23:16 ` Rob Herring
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20160523204846.GA16081@rob-hp-laptop \
--to=robh@kernel.org \
--cc=dalias@libc.org \
--cc=devicetree@vger.kernel.org \
--cc=galak@codeaurora.org \
--cc=ijc+devicetree@hellion.org.uk \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-sh@vger.kernel.org \
--cc=mark.rutland@arm.com \
--cc=pawel.moll@arm.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).