From: Dong Aisheng <dongas86@gmail.com>
To: Lothar Wa??mann <LW@KARO-electronics.de>
Cc: Dong Aisheng <aisheng.dong@nxp.com>,
anson.huang@nxp.com, mturquette@baylibre.com,
sboyd@codeaurora.org, linux-kernel@vger.kernel.org,
shawnguo@kernel.org, linux-clk@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 05/11] clk: imx: refine the powerup_set bit of clk-pllv3
Date: Sun, 12 Jun 2016 19:56:22 +0800 [thread overview]
Message-ID: <20160612115622.GD32690@shlinux2> (raw)
In-Reply-To: <20160609094328.136b7bf8@ipc1.ka-ro>
On Thu, Jun 09, 2016 at 09:43:28AM +0200, Lothar Wa??mann wrote:
> Hi,
>
> On Wed, 8 Jun 2016 22:33:34 +0800 Dong Aisheng wrote:
> > There's a powerdown bit already, so let's change the name of
> > powerup_set bit to power_invert to reflects the power polarity
> > to make it less confusing.
> >
> > Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
> > ---
> > drivers/clk/imx/clk-pllv3.c | 14 +++++++-------
> > 1 file changed, 7 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c
> > index eea2b1b3791e..3fdfb6d2cc71 100644
> > --- a/drivers/clk/imx/clk-pllv3.c
> > +++ b/drivers/clk/imx/clk-pllv3.c
> > @@ -29,8 +29,8 @@
> > * struct clk_pllv3 - IMX PLL clock version 3
> > * @clk_hw: clock source
> > * @base: base address of PLL registers
> > - * @powerup_set: set POWER bit to power up the PLL
> > - * @powerdown: pll powerdown offset bit
> > + * @powerdown: pll powerdown bit offset
> > + * @power_invert: set powerdown bit to power up the PLL
> s/set/clear/ ?
>
It is set.
By default set the powerdown bit will powerdown the PLL according
to spec.
However, for IMX_PLLV3_USB, it's actually power up the PLL,
so the power_invert reflect such using.
Regards
Dong Aisheng
>
>
> Lothar Wa??mann
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2016-06-12 12:02 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-08 14:33 [PATCH 01/11] clk: imx: clk-pllv3: fix incorrect handle of enet powerdown bit Dong Aisheng
2016-06-08 14:33 ` [PATCH 02/11] clk: imx: correct AV PLL rate formula Dong Aisheng
2016-06-12 11:30 ` Shawn Guo
2016-06-08 14:33 ` [PATCH 03/11] clk: imx7d: correct dram root clk parent select Dong Aisheng
2016-06-12 11:31 ` Shawn Guo
2016-06-08 14:33 ` [PATCH 04/11] clk: imx: correct dram pll type Dong Aisheng
2016-06-12 11:33 ` Shawn Guo
2016-06-08 14:33 ` [PATCH 05/11] clk: imx: refine the powerup_set bit of clk-pllv3 Dong Aisheng
2016-06-09 7:43 ` Lothar Waßmann
2016-06-12 11:56 ` Dong Aisheng [this message]
2016-06-12 11:36 ` Shawn Guo
2016-06-12 11:51 ` Dong Aisheng
2016-06-12 12:13 ` Dong Aisheng
2016-06-12 13:29 ` Shawn Guo
2016-06-12 14:51 ` Dong Aisheng
2016-06-13 7:37 ` [PATCH V2 1/1] clk: imx: refine the powerdown " Dong Aisheng
2016-06-13 11:42 ` kbuild test robot
2016-06-13 12:24 ` [PATCH V3 " Dong Aisheng
2016-06-16 1:05 ` Shawn Guo
2016-06-08 14:33 ` [PATCH 06/11] clk: imx6ul: fix gpt2 clock names Dong Aisheng
2016-06-12 11:41 ` Shawn Guo
2016-06-12 11:52 ` Dong Aisheng
2016-06-13 7:38 ` [PATCH V2 1/1] " Dong Aisheng
2016-06-16 1:06 ` Shawn Guo
2016-06-08 14:33 ` [PATCH 07/11] clk: imx6ul: fix pll clock parents Dong Aisheng
2016-06-12 11:43 ` Shawn Guo
2016-06-12 11:52 ` Dong Aisheng
2016-06-12 12:19 ` Dong Aisheng
2016-06-12 13:22 ` Shawn Guo
2016-06-08 14:33 ` [PATCH 08/11] clk: imx6q: " Dong Aisheng
2016-06-08 14:33 ` [PATCH 09/11] clk: imx6sx: " Dong Aisheng
2016-06-08 14:33 ` [PATCH 10/11] clk: imx6sl: " Dong Aisheng
2016-06-08 14:33 ` [PATCH 11/11] clk: imx7d: " Dong Aisheng
2016-06-12 14:56 ` [PATCH 01/11] clk: imx: clk-pllv3: fix incorrect handle of enet powerdown bit Dong Aisheng
2016-06-13 2:54 ` Shawn Guo
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