From: Lee Jones <lee.jones@linaro.org>
To: Andrew Jeffery <andrew@aj.id.au>, arnd@arndb.de
Cc: Linus Walleij <linus.walleij@linaro.org>,
Joel Stanley <joel@jms.id.au>,
Mark Rutland <mark.rutland@arm.com>,
Rob Herring <robh+dt@kernel.org>,
linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH v2 2/6] mfd: dt: Add bindings for the Aspeed SoC Display Controller (GFX)
Date: Fri, 18 Nov 2016 18:47:15 +0000 [thread overview]
Message-ID: <20161118184715.GG19884@dell.home> (raw)
In-Reply-To: <1478097481-14895-3-git-send-email-andrew@aj.id.au>
On Thu, 03 Nov 2016, Andrew Jeffery wrote:
> The Aspeed SoC Display Controller is presented as a syscon device to
> arbitrate access by display and pinmux drivers. Video pinmux
> configuration on fifth generation SoCs depends on bits in both the
> System Control Unit and the Display Controller.
>
> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
> ---
> Documentation/devicetree/bindings/mfd/aspeed-gfx.txt | 17 +++++++++++++++++
> 1 file changed, 17 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mfd/aspeed-gfx.txt
Same here.
> diff --git a/Documentation/devicetree/bindings/mfd/aspeed-gfx.txt b/Documentation/devicetree/bindings/mfd/aspeed-gfx.txt
> new file mode 100644
> index 000000000000..aea5370efd97
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mfd/aspeed-gfx.txt
> @@ -0,0 +1,17 @@
> +* Device tree bindings for Aspeed SoC Display Controller (GFX)
> +
> +The Aspeed SoC Display Controller primarily does as its name suggests, but also
> +participates in pinmux requests on the g5 SoCs. It is therefore considered a
> +syscon device.
> +
> +Required properties:
> +- compatible: "aspeed,ast2500-gfx", "syscon"
> +- reg: contains offset/length value of the GFX memory
> + region.
> +
> +Example:
> +
> +gfx: display@1e6e6000 {
> + compatible = "aspeed,ast2500-gfx", "syscon";
> + reg = <0x1e6e6000 0x1000>;
> +};
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
next prev parent reply other threads:[~2016-11-18 18:44 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-11-02 14:37 [PATCH v2 0/6] pinctrl: aspeed: Fixes for g5, implement remaining pins Andrew Jeffery
2016-11-02 14:37 ` [PATCH v2 1/6] pinctrl-aspeed-g5: Never set SCU90[6] Andrew Jeffery
2016-11-03 22:59 ` Joel Stanley
2016-11-07 9:34 ` Linus Walleij
2016-11-07 22:42 ` Andrew Jeffery
2016-11-07 9:32 ` Linus Walleij
2016-11-02 14:37 ` [PATCH v2 2/6] mfd: dt: Add bindings for the Aspeed SoC Display Controller (GFX) Andrew Jeffery
2016-11-09 18:26 ` Rob Herring
2016-11-10 3:19 ` Joel Stanley
2016-11-10 17:40 ` Rob Herring
2016-11-18 18:47 ` Lee Jones [this message]
2016-11-02 14:37 ` [PATCH v2 3/6] mfd: dt: Add bindings for the Aspeed LPC Host Controller (LPCHC) Andrew Jeffery
2016-11-03 23:06 ` Joel Stanley
2016-11-04 3:45 ` Andrew Jeffery
2016-11-18 18:44 ` Lee Jones
2016-11-18 18:45 ` Lee Jones
2016-11-22 3:25 ` Andrew Jeffery
2016-11-02 14:37 ` [PATCH v2 4/6] pinctrl: aspeed: Read and write bits in LPCHC and GFX controllers Andrew Jeffery
2016-11-03 23:24 ` Joel Stanley
2016-11-04 3:59 ` Andrew Jeffery
2016-11-09 18:26 ` Rob Herring
2016-11-09 23:50 ` Andrew Jeffery
2016-11-02 14:38 ` [PATCH v2 5/6] pinctrl: aspeed-g4: Add mux configuration for all pins Andrew Jeffery
2016-11-02 14:38 ` [PATCH v2 6/6] pinctrl: aspeed-g5: " Andrew Jeffery
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