From: Chen-Yu Tsai <wens@csie.org>
To: Maxime Ripard <maxime.ripard@free-electrons.com>,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@codeaurora.org>
Cc: Chen-Yu Tsai <wens@csie.org>,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-sunxi@googlegroups.com
Subject: [PATCH v2 04/10] clk: sunxi-ng: Support separately grouped PLL lock status register
Date: Sat, 28 Jan 2017 20:22:33 +0800 [thread overview]
Message-ID: <20170128122239.4480-5-wens@csie.org> (raw)
In-Reply-To: <20170128122239.4480-1-wens@csie.org>
On the Allwinner A80 SoC, the PLL lock status indicators are grouped
together in a separate register, as opposed to being scattered in each
PLL's configuration register.
Add a flag to support this.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
drivers/clk/sunxi-ng/ccu_common.c | 9 +++++++--
drivers/clk/sunxi-ng/ccu_common.h | 2 ++
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu_common.c b/drivers/clk/sunxi-ng/ccu_common.c
index 51d4bac97ab3..6986e11e91b0 100644
--- a/drivers/clk/sunxi-ng/ccu_common.c
+++ b/drivers/clk/sunxi-ng/ccu_common.c
@@ -25,13 +25,18 @@ static DEFINE_SPINLOCK(ccu_lock);
void ccu_helper_wait_for_lock(struct ccu_common *common, u32 lock)
{
+ void __iomem *addr;
u32 reg;
if (!lock)
return;
- WARN_ON(readl_relaxed_poll_timeout(common->base + common->reg, reg,
- reg & lock, 100, 70000));
+ if (common->features & CCU_FEATURE_LOCK_REG)
+ addr = common->base + common->lock_reg;
+ else
+ addr = common->base + common->reg;
+
+ WARN_ON(readl_relaxed_poll_timeout(addr, reg, reg & lock, 100, 70000));
}
int sunxi_ccu_probe(struct device_node *node, void __iomem *reg,
diff --git a/drivers/clk/sunxi-ng/ccu_common.h b/drivers/clk/sunxi-ng/ccu_common.h
index cdd69eb2e0b9..73d81dc58fc5 100644
--- a/drivers/clk/sunxi-ng/ccu_common.h
+++ b/drivers/clk/sunxi-ng/ccu_common.h
@@ -22,6 +22,7 @@
#define CCU_FEATURE_FIXED_PREDIV BIT(2)
#define CCU_FEATURE_FIXED_POSTDIV BIT(3)
#define CCU_FEATURE_ALL_PREDIV BIT(4)
+#define CCU_FEATURE_LOCK_REG BIT(5)
struct device_node;
@@ -57,6 +58,7 @@ struct device_node;
struct ccu_common {
void __iomem *base;
u16 reg;
+ u16 lock_reg;
u32 prediv;
unsigned long features;
--
2.11.0
next prev parent reply other threads:[~2017-01-28 12:29 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-01-28 12:22 [PATCH v2 00/10] clk: sunxi-ng: Add support for A80 CCUs Chen-Yu Tsai
2017-01-28 12:22 ` [PATCH v2 01/10] clk: sunxi-ng: mux: Fix determine_rate for mux clocks with pre-dividers Chen-Yu Tsai
2017-01-28 12:22 ` [PATCH v2 02/10] clk: sunxi-ng: mux: honor CLK_SET_RATE_NO_REPARENT flag Chen-Yu Tsai
2017-01-28 12:22 ` [PATCH v2 03/10] clk: sunxi-ng: mux: Get closest parent rate possible with CLK_SET_RATE_PARENT Chen-Yu Tsai
2017-01-28 12:22 ` Chen-Yu Tsai [this message]
2017-01-28 12:22 ` [PATCH v2 05/10] clk: sunxi-ng: Add A80 CCU Chen-Yu Tsai
2017-01-28 12:22 ` [PATCH v2 06/10] clk: sunxi-ng: Add A80 USB CCU Chen-Yu Tsai
2017-01-28 12:22 ` [PATCH v2 07/10] clk: sunxi-ng: Add A80 Display Engine CCU Chen-Yu Tsai
2017-01-28 12:22 ` [PATCH v2 08/10] ARM: dts: sun8i-a23-q8-tablet: Drop pinmux setting for codec PA gpio Chen-Yu Tsai
2017-01-28 12:22 ` [PATCH v2 09/10] ARM: dts: sunxi: Remove no longer used pinctrl/sun4i-a10.h header Chen-Yu Tsai
2017-01-28 12:22 ` [PATCH v2 10/10] ARM: dts: sun9i: Switch to new clock bindings Chen-Yu Tsai
2017-01-30 7:42 ` [PATCH v2 00/10] clk: sunxi-ng: Add support for A80 CCUs Maxime Ripard
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