From: Yixun Lan <yixun.lan@amlogic.com>
To: Neil Armstrong <narmstrong@baylibre.com>,
Jerome Brunet <jbrunet@baylibre.com>
Cc: Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@codeaurora.org>,
Rob Herring <robh@kernel.org>, Carlo Caione <carlo@caione.org>,
Kevin Hilman <khilman@baylibre.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
Yixun Lan <yixun.lan@amlogic.com>,
Qiufang Dai <qiufang.dai@amlogic.com>,
Jian Hu <jian.hu@amlogic.com>,
<linux-amlogic@lists.infradead.org>, <linux-clk@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>
Subject: [PATCH 1/2] dt-bindings: clock: reset: Add AXG AO Clock and Reset Bindings
Date: Fri, 9 Feb 2018 15:00:25 +0800 [thread overview]
Message-ID: <20180209070026.193879-2-yixun.lan@amlogic.com> (raw)
In-Reply-To: <20180209070026.193879-1-yixun.lan@amlogic.com>
Add dt-bindings headers for the Meson-AXG's AO clock and
reset controller.
CC: <devicetree@vger.kernel.org>
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
---
include/dt-bindings/clock/axg-aoclkc.h | 26 ++++++++++++++++++++++++++
include/dt-bindings/reset/axg-aoclkc.h | 20 ++++++++++++++++++++
2 files changed, 46 insertions(+)
create mode 100644 include/dt-bindings/clock/axg-aoclkc.h
create mode 100644 include/dt-bindings/reset/axg-aoclkc.h
diff --git a/include/dt-bindings/clock/axg-aoclkc.h b/include/dt-bindings/clock/axg-aoclkc.h
new file mode 100644
index 000000000000..78683abb4247
--- /dev/null
+++ b/include/dt-bindings/clock/axg-aoclkc.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD) */
+/*
+ * Copyright (c) 2016 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Qiufang Dai <qiufang.dai@amlogic.com>
+ */
+
+#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK
+#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK
+
+#define CLKID_AO_REMOTE 0
+#define CLKID_AO_I2C_MASTER 1
+#define CLKID_AO_I2C_SLAVE 2
+#define CLKID_AO_UART1 3
+#define CLKID_AO_UART2 4
+#define CLKID_AO_IR_BLASTER 5
+#define CLKID_AO_SAR_ADC 6
+#define CLKID_AO_CLK81 7
+#define CLKID_AO_SAR_ADC_SEL 8
+#define CLKID_AO_SAR_ADC_DIV 9
+#define CLKID_AO_SAR_ADC_CLK 10
+#define CLKID_AO_ALT_XTAL 11
+
+#endif
diff --git a/include/dt-bindings/reset/axg-aoclkc.h b/include/dt-bindings/reset/axg-aoclkc.h
new file mode 100644
index 000000000000..307f58161bbb
--- /dev/null
+++ b/include/dt-bindings/reset/axg-aoclkc.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD) */
+/*
+ * Copyright (c) 2016 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Qiufang Dai <qiufang.dai@amlogic.com>
+ */
+
+#ifndef DT_BINDINGS_RESET_AMLOGIC_MESON_AXG_AOCLK
+#define DT_BINDINGS_RESET_AMLOGIC_MESON_AXG_AOCLK
+
+#define RESET_AO_REMOTE 0
+#define RESET_AO_I2C_MASTER 1
+#define RESET_AO_I2C_SLAVE 2
+#define RESET_AO_UART1 3
+#define RESET_AO_UART2 4
+#define RESET_AO_IR_BLASTER 5
+
+#endif
--
2.15.1
next prev parent reply other threads:[~2018-02-09 7:01 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-02-09 7:00 [PATCH 0/2] clk: meson-axg: Add AO Cloclk and Reset driver Yixun Lan
2018-02-09 7:00 ` Yixun Lan [this message]
2018-02-09 11:07 ` [PATCH 1/2] dt-bindings: clock: reset: Add AXG AO Clock and Reset Bindings Philippe Ombredanne
2018-03-23 14:06 ` Yixun Lan
2018-02-09 7:00 ` [PATCH 2/2] clk: meson-axg: Add AO Clock and Reset controller driver Yixun Lan
2018-02-12 15:32 ` Jerome Brunet
2018-02-13 14:51 ` Jerome Brunet
2018-03-23 14:13 ` Yixun Lan
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