From: Wu Hao <hao.wu@intel.com>
To: Alan Tull <atull@kernel.org>
Cc: Moritz Fischer <mdf@kernel.org>,
linux-fpga@vger.kernel.org,
linux-kernel <linux-kernel@vger.kernel.org>,
linux-api@vger.kernel.org, "Kang, Luwei" <luwei.kang@intel.com>,
"Zhang, Yi Z" <yi.z.zhang@intel.com>,
Tim Whisonant <tim.whisonant@intel.com>,
Enno Luebbers <enno.luebbers@intel.com>,
Shiva Rao <shiva.rao@intel.com>,
Christopher Rauer <christopher.rauer@intel.com>,
Xiao Guangrong <guangrong.xiao@linux.intel.com>
Subject: Re: [PATCH v4 20/24] fpga: dfl: add FPGA Accelerated Function Unit driver basic framework
Date: Fri, 6 Apr 2018 19:05:36 +0800 [thread overview]
Message-ID: <20180406110536.GC32345@hao-dev> (raw)
In-Reply-To: <CANk1AXSgd4ySjCqiTyMA4vaOq4jByhLOot02GCLMmgoQSye49Q@mail.gmail.com>
On Thu, Apr 05, 2018 at 01:26:57PM -0500, Alan Tull wrote:
> On Tue, Feb 13, 2018 at 3:24 AM, Wu Hao <hao.wu@intel.com> wrote:
>
> Hi Hao,
>
> One minor thing below.
>
> > On DFL FPGA devices, the Accelerated Function Unit (AFU), can be
> > reprogrammed for different functions. It connects to the FPGA
> > infrastructure("blue bistream") via a Port. Port CSRs are implemented
> > separately from the AFU CSRs to provide control and status of the Port.
> > Once valid green bitstream is programmed into the AFU, it allows access
> > to the AFU CSRs in the AFU MMIO space.
> >
> > This patch only implements basic driver framework for AFU, including
> > device file operation framework.
> >
> > Signed-off-by: Tim Whisonant <tim.whisonant@intel.com>
> > Signed-off-by: Enno Luebbers <enno.luebbers@intel.com>
> > Signed-off-by: Shiva Rao <shiva.rao@intel.com>
> > Signed-off-by: Christopher Rauer <christopher.rauer@intel.com>
> > Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
> > Signed-off-by: Wu Hao <hao.wu@intel.com>
> > ---
> > v3: rename driver to dfl-afu-main.c
> > v4: rename to dfl-port and fix SPDX license issue.
> > ---
> > drivers/fpga/Kconfig | 9 +++
> > drivers/fpga/Makefile | 2 +
> > drivers/fpga/dfl-afu-main.c | 159 ++++++++++++++++++++++++++++++++++++++++++++
> > 3 files changed, 170 insertions(+)
> > create mode 100644 drivers/fpga/dfl-afu-main.c
> >
> > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> > index 65d54a4..4c6b45f 100644
> > --- a/drivers/fpga/Kconfig
> > +++ b/drivers/fpga/Kconfig
> > @@ -168,6 +168,15 @@ config FPGA_DFL_FME_REGION
> > help
> > Say Y to enable FPGA Region driver for FPGA Management Engine.
> >
> > +config FPGA_DFL_AFU
> > + tristate "FPGA DFL AFU Driver"
> > + depends on FPGA_DFL
> > + help
> > + This is the driver for FPGA Accelerated Function Unit (AFU) which
> > + implements AFU and Port management features. A User AFU connects
> > + to the FPGA infrastructure via a Port. There may be more than 1
> > + Port/AFU per DFL based FPGA device.
> > +
> > config FPGA_DFL_PCI
> > tristate "FPGA Device Feature List (DFL) PCIe Device Driver"
> > depends on PCI && FPGA_DFL
> > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
> > index 163894e..5c9607b 100644
> > --- a/drivers/fpga/Makefile
> > +++ b/drivers/fpga/Makefile
> > @@ -34,8 +34,10 @@ obj-$(CONFIG_FPGA_DFL_FME) += dfl-fme.o
> > obj-$(CONFIG_FPGA_DFL_FME_MGR) += dfl-fme-mgr.o
> > obj-$(CONFIG_FPGA_DFL_FME_BRIDGE) += dfl-fme-br.o
> > obj-$(CONFIG_FPGA_DFL_FME_REGION) += dfl-fme-region.o
> > +obj-$(CONFIG_FPGA_DFL_AFU) += dfl-afu.o
> >
> > dfl-fme-objs := dfl-fme-main.o dfl-fme-pr.o
> > +dfl-afu-objs := dfl-afu-main.o
> >
> > # Drivers for FPGAs which implement DFL
> > obj-$(CONFIG_FPGA_DFL_PCI) += dfl-pci.o
> > diff --git a/drivers/fpga/dfl-afu-main.c b/drivers/fpga/dfl-afu-main.c
> > new file mode 100644
> > index 0000000..70db28c
> > --- /dev/null
> > +++ b/drivers/fpga/dfl-afu-main.c
> > @@ -0,0 +1,159 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Driver for FPGA Accelerated Function Unit (AFU)
> > + *
> > + * Copyright (C) 2017 Intel Corporation, Inc.
> > + *
> > + * Authors:
> > + * Wu Hao <hao.wu@intel.com>
> > + * Xiao Guangrong <guangrong.xiao@linux.intel.com>
> > + * Joseph Grecco <joe.grecco@intel.com>
> > + * Enno Luebbers <enno.luebbers@intel.com>
> > + * Tim Whisonant <tim.whisonant@intel.com>
> > + * Ananda Ravuri <ananda.ravuri@intel.com>
> > + * Henry Mitchel <henry.mitchel@intel.com>
> > + */
> > +
> > +#include <linux/kernel.h>
> > +#include <linux/module.h>
> > +
> > +#include "dfl.h"
> > +
> > +static int port_hdr_init(struct platform_device *pdev, struct feature *feature)
> > +{
> > + dev_dbg(&pdev->dev, "PORT HDR Init.\n");
> > +
> > + return 0;
> > +}
> > +
> > +static void port_hdr_uinit(struct platform_device *pdev,
> > + struct feature *feature)
> > +{
> > + dev_dbg(&pdev->dev, "PORT HDR UInit.\n");
> > +}
> > +
> > +static const struct feature_ops port_hdr_ops = {
> > + .init = port_hdr_init,
> > + .uinit = port_hdr_uinit,
> > +};
> > +
> > +static struct feature_driver port_feature_drvs[] = {
> > + {
> > + .id = PORT_FEATURE_ID_HEADER,
> > + .ops = &port_hdr_ops,
> > + },
> > + {
> > + .ops = NULL,
> > + }
> > +};
> > +
> > +static int afu_open(struct inode *inode, struct file *filp)
> > +{
> > + struct platform_device *fdev = fpga_inode_to_feature_dev(inode);
> > + struct feature_platform_data *pdata;
> > + int ret;
> > +
> > + pdata = dev_get_platdata(&fdev->dev);
> > + if (WARN_ON(!pdata))
> > + return -ENODEV;
> > +
> > + ret = feature_dev_use_begin(pdata);
> > + if (ret)
> > + return ret;
> > +
> > + dev_dbg(&fdev->dev, "Device File Open\n");
> > + filp->private_data = fdev;
> > +
> > + return 0;
> > +}
> > +
> > +static int afu_release(struct inode *inode, struct file *filp)
> > +{
> > + struct platform_device *pdev = filp->private_data;
> > + struct feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
> > +
> > + dev_dbg(&pdev->dev, "Device File Release\n");
> > +
> > + feature_dev_use_end(pdata);
> > +
> > + return 0;
> > +}
> > +
> > +static long afu_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
> > +{
> > + struct platform_device *pdev = filp->private_data;
> > + struct feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
> > + struct feature *f;
> > + long ret;
> > +
> > + dev_dbg(&pdev->dev, "%s cmd 0x%x\n", __func__, cmd);
> > +
> > + switch (cmd) {
> > + default:
> > + /*
> > + * Let sub-feature's ioctl function to handle the cmd
> > + * Sub-feature's ioctl returns -ENODEV when cmd is not
> > + * handled in this sub feature, and returns 0 and other
> > + * error code if cmd is handled.
> > + */
> > + fpga_dev_for_each_feature(pdata, f)
> > + if (f->ops && f->ops->ioctl) {
> > + ret = f->ops->ioctl(pdev, f, cmd, arg);
> > + if (ret == -ENODEV)
> > + continue;
> > + else
> > + return ret;
>
> The continue..else isn't needed. Could just be
> if (ret != -ENODEV)
> return ret;
Agree, will fix this in the next version. Thanks.
Hao
>
> Thanks,
> Alan
>
> > + }
> > + }
> > +
> > + return -EINVAL;
> > +}
> > +
> > +static const struct file_operations afu_fops = {
> > + .owner = THIS_MODULE,
> > + .open = afu_open,
> > + .release = afu_release,
> > + .unlocked_ioctl = afu_ioctl,
> > +};
> > +
> > +static int afu_probe(struct platform_device *pdev)
> > +{
> > + int ret;
> > +
> > + dev_dbg(&pdev->dev, "%s\n", __func__);
> > +
> > + ret = fpga_dev_feature_init(pdev, port_feature_drvs);
> > + if (ret)
> > + return ret;
> > +
> > + ret = fpga_register_dev_ops(pdev, &afu_fops, THIS_MODULE);
> > + if (ret)
> > + fpga_dev_feature_uinit(pdev);
> > +
> > + return ret;
> > +}
> > +
> > +static int afu_remove(struct platform_device *pdev)
> > +{
> > + dev_dbg(&pdev->dev, "%s\n", __func__);
> > +
> > + fpga_dev_feature_uinit(pdev);
> > + fpga_unregister_dev_ops(pdev);
> > +
> > + return 0;
> > +}
> > +
> > +static struct platform_driver afu_driver = {
> > + .driver = {
> > + .name = FPGA_FEATURE_DEV_PORT,
> > + },
> > + .probe = afu_probe,
> > + .remove = afu_remove,
> > +};
> > +
> > +module_platform_driver(afu_driver);
> > +
> > +MODULE_DESCRIPTION("FPGA Accelerated Function Unit driver");
> > +MODULE_AUTHOR("Intel Corporation");
> > +MODULE_LICENSE("GPL v2");
> > +MODULE_ALIAS("platform:dfl-port");
> > --
> > 2.7.4
> >
next prev parent reply other threads:[~2018-04-06 11:15 UTC|newest]
Thread overview: 93+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-02-13 9:24 [PATCH v4 00/24] FPGA Device Feature List (DFL) Device Drivers Wu Hao
2018-02-13 9:24 ` [PATCH v4 01/24] docs: fpga: add a document for FPGA Device Feature List (DFL) Framework Overview Wu Hao
2018-02-26 22:48 ` Alan Tull
2018-02-27 2:12 ` Wu Hao
2018-02-13 9:24 ` [PATCH v4 02/24] fpga: mgr: add region_id to fpga_image_info Wu Hao
2018-02-13 9:24 ` [PATCH v4 03/24] fpga: mgr: add status for fpga-manager Wu Hao
2018-02-14 15:55 ` Alan Tull
2018-02-15 9:42 ` Wu, Hao
2018-02-14 20:55 ` Moritz Fischer
2018-02-13 9:24 ` [PATCH v4 04/24] fpga: add device feature list support Wu Hao
2018-03-21 23:54 ` Alan Tull
2018-03-22 4:40 ` Wu Hao
2018-03-22 21:31 ` Alan Tull
2018-03-23 4:33 ` Wu Hao
2018-03-26 17:21 ` Alan Tull
2018-03-27 2:35 ` Wu Hao
2018-03-29 21:57 ` Alan Tull
2018-04-02 4:22 ` Wu Hao
2018-04-02 19:06 ` Alan Tull
2018-04-03 1:36 ` Wu Hao
2018-04-04 20:06 ` Alan Tull
2018-04-06 11:01 ` Wu Hao
2018-02-13 9:24 ` [PATCH v4 05/24] fpga: dfl: add chardev support for feature devices Wu Hao
2018-02-13 9:24 ` [PATCH v4 06/24] fpga: dfl: adds fpga_cdev_find_port Wu Hao
2018-02-14 16:24 ` Alan Tull
2018-02-15 9:46 ` Wu, Hao
2018-02-14 20:55 ` Moritz Fischer
2018-02-13 9:24 ` [PATCH v4 07/24] fpga: dfl: add feature device infrastructure Wu Hao
2018-02-14 21:03 ` Moritz Fischer
2018-02-14 21:13 ` Alan Tull
2018-02-15 10:05 ` Wu, Hao
2018-02-15 19:49 ` Moritz Fischer
2018-02-18 2:15 ` Wu, Hao
2018-02-13 9:24 ` [PATCH v4 08/24] fpga: add FPGA DFL PCIe device driver Wu Hao
2018-03-13 16:05 ` Alan Tull
2018-03-15 18:49 ` Moritz Fischer
2018-03-16 4:29 ` Wu Hao
2018-02-13 9:24 ` [PATCH v4 09/24] fpga: dfl-pci: add enumeration for feature devices Wu Hao
2018-03-13 18:30 ` Alan Tull
2018-03-14 5:21 ` Wu Hao
2018-03-14 14:48 ` Alan Tull
2018-02-13 9:24 ` [PATCH v4 10/24] fpga: dfl: add FPGA Management Engine driver basic framework Wu Hao
2018-04-05 18:35 ` Alan Tull
2018-04-06 11:04 ` Wu Hao
2018-02-13 9:24 ` [PATCH v4 11/24] fpga: dfl: fme: add header sub feature support Wu Hao
2018-02-14 16:36 ` Alan Tull
2018-02-13 9:24 ` [PATCH v4 12/24] fpga: dfl: fme: add FPGA_GET_API_VERSION/CHECK_EXTENSION ioctls support Wu Hao
2018-03-19 18:29 ` Alan Tull
2018-03-20 6:46 ` Wu Hao
2018-02-13 9:24 ` [PATCH v4 13/24] fpga: region: add compat_id support Wu Hao
2018-02-28 22:55 ` Alan Tull
2018-03-01 6:17 ` Wu Hao
2018-03-05 19:42 ` Alan Tull
2018-03-06 0:56 ` Wu Hao
2018-02-13 9:24 ` [PATCH v4 14/24] fpga: dfl: fme: add partial reconfiguration sub feature support Wu Hao
2018-03-05 22:46 ` Alan Tull
2018-03-06 2:08 ` Wu Hao
2018-03-06 18:29 ` Alan Tull
2018-03-07 4:39 ` Wu Hao
2018-03-11 20:09 ` matthew.gerlach
2018-03-12 4:29 ` Wu Hao
2018-03-12 18:53 ` Alan Tull
2018-03-12 21:36 ` matthew.gerlach
2018-03-13 1:07 ` Wu Hao
2018-02-13 9:24 ` [PATCH v4 15/24] fpga: dfl-fme-pr: add compat_id support for dfl-fme-region platform device Wu Hao
2018-02-28 23:06 ` Alan Tull
2018-03-01 5:49 ` Wu Hao
2018-03-01 15:59 ` Alan Tull
2018-03-01 15:55 ` Wu Hao
2018-02-13 9:24 ` [PATCH v4 16/24] fpga: dfl: add fpga manager platform driver for FME Wu Hao
2018-03-20 20:32 ` Alan Tull
2018-03-21 2:50 ` Wu Hao
2018-03-21 16:55 ` Moritz Fischer
2018-03-22 6:07 ` Wu Hao
2018-04-05 18:45 ` Alan Tull
2018-04-06 11:11 ` Wu Hao
2018-02-13 9:24 ` [PATCH v4 17/24] fpga: dfl: add fpga bridge " Wu Hao
2018-02-13 9:24 ` [PATCH v4 18/24] fpga: dfl: add fpga region " Wu Hao
2018-02-13 9:24 ` [PATCH v4 19/24] fpga: dfl-fme-region: add compat_id support Wu Hao
2018-02-13 9:24 ` [PATCH v4 20/24] fpga: dfl: add FPGA Accelerated Function Unit driver basic framework Wu Hao
2018-03-19 18:40 ` Alan Tull
2018-04-05 18:26 ` Alan Tull
2018-04-06 11:05 ` Wu Hao [this message]
2018-02-13 9:24 ` [PATCH v4 21/24] fpga: dfl: afu: add header sub feature support Wu Hao
2018-02-13 9:24 ` [PATCH v4 22/24] fpga: dfl: afu: add FPGA_GET_API_VERSION/CHECK_EXTENSION ioctls support Wu Hao
2018-02-13 9:24 ` [PATCH v4 23/24] fpga: dfl: afu: add user afu sub feature support Wu Hao
2018-03-19 20:10 ` Alan Tull
2018-03-20 7:10 ` Wu Hao
2018-03-20 18:17 ` Alan Tull
2018-03-21 3:00 ` Wu Hao
2018-03-21 23:50 ` Alan Tull
2018-03-22 4:41 ` Wu Hao
2018-02-13 9:24 ` [PATCH v4 24/24] fpga: dfl: afu: add FPGA_PORT_DMA_MAP/UNMAP ioctls support Wu Hao
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20180406110536.GC32345@hao-dev \
--to=hao.wu@intel.com \
--cc=atull@kernel.org \
--cc=christopher.rauer@intel.com \
--cc=enno.luebbers@intel.com \
--cc=guangrong.xiao@linux.intel.com \
--cc=linux-api@vger.kernel.org \
--cc=linux-fpga@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=luwei.kang@intel.com \
--cc=mdf@kernel.org \
--cc=shiva.rao@intel.com \
--cc=tim.whisonant@intel.com \
--cc=yi.z.zhang@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).