From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B8ED2C46470 for ; Tue, 7 Aug 2018 17:00:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7A58D21884 for ; Tue, 7 Aug 2018 17:00:14 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7A58D21884 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=bootlin.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389683AbeHGTPZ (ORCPT ); Tue, 7 Aug 2018 15:15:25 -0400 Received: from mail.bootlin.com ([62.4.15.54]:36209 "EHLO mail.bootlin.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388481AbeHGTPZ (ORCPT ); Tue, 7 Aug 2018 15:15:25 -0400 Received: by mail.bootlin.com (Postfix, from userid 110) id 47BE9209C2; Tue, 7 Aug 2018 19:00:08 +0200 (CEST) Received: from bbrezillon (91-160-177-164.subs.proxad.net [91.160.177.164]) by mail.bootlin.com (Postfix) with ESMTPSA id 4AB61207D4; Tue, 7 Aug 2018 18:59:57 +0200 (CEST) Date: Tue, 7 Aug 2018 18:59:58 +0200 From: Boris Brezillon To: Janusz Krzysztofik Cc: Linus Walleij , Jonathan Corbet , Miquel Raynal , Richard Weinberger , David Woodhouse , Brian Norris , Marek Vasut , Tony Lindgren , Aaro Koskinen , linux-arm-kernel@lists.infradead.org, linux-omap@vger.kernel.org, linux-mtd@lists.infradead.org, linux-doc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [RFC PATCH v2 03/12] ARM: OMAP1: ams-delta: Provide GPIO lookup table for NAND data port Message-ID: <20180807185958.2fc6e22b@bbrezillon> In-Reply-To: <20180806222918.12644-4-jmkrzyszt@gmail.com> References: <20180718235710.18242-1-jmkrzyszt@gmail.com> <20180806222918.12644-1-jmkrzyszt@gmail.com> <20180806222918.12644-4-jmkrzyszt@gmail.com> X-Mailer: Claws Mail 3.15.0-dirty (GTK+ 2.24.31; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 7 Aug 2018 00:29:09 +0200 Janusz Krzysztofik wrote: > Data port used by Amstrad Delta NAND driver is actually an OMAP MPUIO > device, already under control of gpio-omap driver. The NAND driver > gets access to the port by ioremapping it and performs read/write > operations. That is done without any proteciton from other users > legally manipulating the port pins over GPIO API. > > The plan is to convert the driver to access the port over GPIO consumer > API. Before that is implemented, the driver can already obtain > exclusive access to the port by requesting an array of its GPIO > descriptors. > > Add respective entries to the NAND GPIO lookup table. > > Signed-off-by: Janusz Krzysztofik Reviewed-by: Boris Brezillon > --- > arch/arm/mach-omap1/board-ams-delta.c | 11 ++++++++++- > 1 file changed, 10 insertions(+), 1 deletion(-) > > diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c > index eedacdfe9725..16f7bbe47607 100644 > --- a/arch/arm/mach-omap1/board-ams-delta.c > +++ b/arch/arm/mach-omap1/board-ams-delta.c > @@ -337,7 +337,8 @@ static struct platform_device ams_delta_nand_device = { > .resource = ams_delta_nand_resources, > }; > > -#define OMAP_GPIO_LABEL "gpio-0-15" > +#define OMAP_GPIO_LABEL "gpio-0-15" > +#define OMAP_MPUIO_LABEL "mpuio" > > static struct gpiod_lookup_table ams_delta_nand_gpio_table = { > .table = { > @@ -349,6 +350,14 @@ static struct gpiod_lookup_table ams_delta_nand_gpio_table = { > GPIO_LOOKUP(LATCH2_LABEL, LATCH2_PIN_NAND_NWE, "nwe", 0), > GPIO_LOOKUP(LATCH2_LABEL, LATCH2_PIN_NAND_ALE, "ale", 0), > GPIO_LOOKUP(LATCH2_LABEL, LATCH2_PIN_NAND_CLE, "cle", 0), > + GPIO_LOOKUP_IDX(OMAP_MPUIO_LABEL, 0, "data", 0, 0), > + GPIO_LOOKUP_IDX(OMAP_MPUIO_LABEL, 1, "data", 1, 0), > + GPIO_LOOKUP_IDX(OMAP_MPUIO_LABEL, 2, "data", 2, 0), > + GPIO_LOOKUP_IDX(OMAP_MPUIO_LABEL, 3, "data", 3, 0), > + GPIO_LOOKUP_IDX(OMAP_MPUIO_LABEL, 4, "data", 4, 0), > + GPIO_LOOKUP_IDX(OMAP_MPUIO_LABEL, 5, "data", 5, 0), > + GPIO_LOOKUP_IDX(OMAP_MPUIO_LABEL, 6, "data", 6, 0), > + GPIO_LOOKUP_IDX(OMAP_MPUIO_LABEL, 7, "data", 7, 0), > { }, > }, > };