From: Quentin Schulz <quentin.schulz@bootlin.com>
To: alexandre.belloni@bootlin.com, ralf@linux-mips.org,
paul.burton@mips.com, jhogan@kernel.org, robh+dt@kernel.org,
mark.rutland@arm.com, davem@davemloft.net, kishon@ti.com,
andrew@lunn.ch, f.fainelli@gmail.com
Cc: allan.nielsen@microchip.com, linux-mips@linux-mips.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
netdev@vger.kernel.org, thomas.petazzoni@bootlin.com,
Quentin Schulz <quentin.schulz@bootlin.com>
Subject: [PATCH net-next v4 02/11] dt-bindings: net: ocelot: remove hsio from the list of register address spaces
Date: Thu, 4 Oct 2018 14:21:59 +0200 [thread overview]
Message-ID: <20181004122208.32272-3-quentin.schulz@bootlin.com> (raw)
In-Reply-To: <20181004122208.32272-1-quentin.schulz@bootlin.com>
HSIO register address space should be handled outside of the MAC
controller as there are some registers for PLL5 configuring,
SerDes/switch port muxing and a thermal sensor IP, so let's remove it.
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
---
Documentation/devicetree/bindings/mips/mscc.txt | 16 ++++++++++++++++
.../devicetree/bindings/net/mscc-ocelot.txt | 9 +++------
2 files changed, 19 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/mips/mscc.txt b/Documentation/devicetree/bindings/mips/mscc.txt
index ae15ec333542..bc817e984628 100644
--- a/Documentation/devicetree/bindings/mips/mscc.txt
+++ b/Documentation/devicetree/bindings/mips/mscc.txt
@@ -41,3 +41,19 @@ Example:
compatible = "mscc,ocelot-cpu-syscon", "syscon";
reg = <0x70000000 0x2c>;
};
+
+o HSIO regs:
+
+The SoC has a few registers (HSIO) handling miscellaneous functionalities:
+configuration and status of PLL5, RCOMP, SyncE, SerDes configurations and
+status, SerDes muxing and a thermal sensor.
+
+Required properties:
+- compatible: Should be "mscc,ocelot-hsio", "syscon", "simple-mfd"
+- reg : Should contain registers location and length
+
+Example:
+ syscon@10d0000 {
+ compatible = "mscc,ocelot-hsio", "syscon", "simple-mfd";
+ reg = <0x10d0000 0x10000>;
+ };
diff --git a/Documentation/devicetree/bindings/net/mscc-ocelot.txt b/Documentation/devicetree/bindings/net/mscc-ocelot.txt
index 0a84711abece..9e5c17d426ce 100644
--- a/Documentation/devicetree/bindings/net/mscc-ocelot.txt
+++ b/Documentation/devicetree/bindings/net/mscc-ocelot.txt
@@ -12,7 +12,6 @@ Required properties:
- "sys"
- "rew"
- "qs"
- - "hsio"
- "qsys"
- "ana"
- "portX" with X from 0 to the number of last port index available on that
@@ -45,7 +44,6 @@ Example:
reg = <0x1010000 0x10000>,
<0x1030000 0x10000>,
<0x1080000 0x100>,
- <0x10d0000 0x10000>,
<0x11e0000 0x100>,
<0x11f0000 0x100>,
<0x1200000 0x100>,
@@ -59,10 +57,9 @@ Example:
<0x1280000 0x100>,
<0x1800000 0x80000>,
<0x1880000 0x10000>;
- reg-names = "sys", "rew", "qs", "hsio", "port0",
- "port1", "port2", "port3", "port4", "port5",
- "port6", "port7", "port8", "port9", "port10",
- "qsys", "ana";
+ reg-names = "sys", "rew", "qs", "port0", "port1", "port2",
+ "port3", "port4", "port5", "port6", "port7",
+ "port8", "port9", "port10", "qsys", "ana";
interrupts = <21 22>;
interrupt-names = "xtr", "inj";
--
2.17.1
next prev parent reply other threads:[~2018-10-04 12:22 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-04 12:21 [PATCH net-next v4 00/11] mscc: ocelot: add support for SerDes muxing configuration Quentin Schulz
2018-10-04 12:21 ` [PATCH net-next v4 01/11] MIPS: mscc: ocelot: make HSIO registers address range a syscon Quentin Schulz
2018-10-04 12:21 ` Quentin Schulz [this message]
2018-10-04 12:22 ` [PATCH net-next v4 03/11] net: mscc: ocelot: get HSIO regmap from syscon Quentin Schulz
2018-10-04 12:22 ` [PATCH net-next v4 04/11] net: mscc: ocelot: move the HSIO header to include/soc Quentin Schulz
2018-10-04 12:22 ` [PATCH net-next v4 05/11] net: mscc: ocelot: simplify register access for PLL5 configuration Quentin Schulz
2018-10-04 12:22 ` [PATCH net-next v4 06/11] phy: add QSGMII and PCIE modes Quentin Schulz
2018-10-04 12:22 ` [PATCH net-next v4 07/11] dt-bindings: phy: add DT binding for Microsemi Ocelot SerDes muxing Quentin Schulz
2018-10-04 12:22 ` [PATCH net-next v4 08/11] MIPS: mscc: ocelot: add SerDes mux DT node Quentin Schulz
2018-10-04 12:22 ` [PATCH net-next v4 09/11] dt-bindings: add constants for Microsemi Ocelot SerDes driver Quentin Schulz
2018-10-04 20:15 ` Florian Fainelli
2018-10-04 12:22 ` [PATCH net-next v4 10/11] phy: add driver for Microsemi Ocelot SerDes muxing Quentin Schulz
2018-10-04 12:22 ` [PATCH net-next v4 11/11] net: mscc: ocelot: make use of SerDes PHYs for handling their configuration Quentin Schulz
2018-10-04 20:16 ` Florian Fainelli
2018-10-05 21:39 ` [PATCH net-next v4 00/11] mscc: ocelot: add support for SerDes muxing configuration David Miller
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20181004122208.32272-3-quentin.schulz@bootlin.com \
--to=quentin.schulz@bootlin.com \
--cc=alexandre.belloni@bootlin.com \
--cc=allan.nielsen@microchip.com \
--cc=andrew@lunn.ch \
--cc=davem@davemloft.net \
--cc=devicetree@vger.kernel.org \
--cc=f.fainelli@gmail.com \
--cc=jhogan@kernel.org \
--cc=kishon@ti.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mips@linux-mips.org \
--cc=mark.rutland@arm.com \
--cc=netdev@vger.kernel.org \
--cc=paul.burton@mips.com \
--cc=ralf@linux-mips.org \
--cc=robh+dt@kernel.org \
--cc=thomas.petazzoni@bootlin.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).