From: Xiaowei Bao <xiaowei.bao@nxp.com>
To: bhelgaas@google.com, robh+dt@kernel.org, mark.rutland@arm.com,
shawnguo@kernel.org, leoyang.li@nxp.com, kishon@ti.com,
lorenzo.pieralisi@arm.com, arnd@arndb.de,
gregkh@linuxfoundation.org, minghuan.Lian@nxp.com,
mingkai.hu@nxp.com, roy.zang@nxp.com,
kstewart@linuxfoundation.org, cyrille.pitchen@free-electrons.com,
pombredanne@nexb.com, shawn.lin@rock-chips.com,
niklas.cassel@axis.com, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linuxppc-dev@lists.ozlabs.org
Cc: Xiaowei Bao <xiaowei.bao@nxp.com>
Subject: [PATCH 4/6] arm64: dts: Add the PCIE EP node in dts
Date: Thu, 25 Oct 2018 19:08:59 +0800 [thread overview]
Message-ID: <20181025110901.5680-4-xiaowei.bao@nxp.com> (raw)
In-Reply-To: <20181025110901.5680-1-xiaowei.bao@nxp.com>
Add the PCIE EP node in dts for ls1046a.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 32 ++++++++++++++++++++++++
1 files changed, 32 insertions(+), 0 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 64d334c..08b4f08 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -655,6 +655,17 @@
status = "disabled";
};
+ pcie_ep@3400000 {
+ compatible = "fsl,ls-pcie-ep";
+ reg = <0x00 0x03400000 0x0 0x00100000
+ 0x40 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "addr_space";
+ num-ib-windows = <6>;
+ num-ob-windows = <6>;
+ num-lanes = <2>;
+ status = "disabled";
+ };
+
pcie@3500000 {
compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";
reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
@@ -681,6 +692,17 @@
status = "disabled";
};
+ pcie_ep@3500000 {
+ compatible = "fsl,ls-pcie-ep";
+ reg = <0x00 0x03500000 0x0 0x00100000
+ 0x48 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "addr_space";
+ num-ib-windows = <6>;
+ num-ob-windows = <6>;
+ num-lanes = <2>;
+ status = "disabled";
+ };
+
pcie@3600000 {
compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";
reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
@@ -707,6 +729,16 @@
status = "disabled";
};
+ pcie_ep@3600000 {
+ compatible = "fsl,ls-pcie-ep";
+ reg = <0x00 0x03600000 0x0 0x00100000
+ 0x50 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "addr_space";
+ num-ib-windows = <6>;
+ num-ob-windows = <6>;
+ num-lanes = <2>;
+ status = "disabled";
+ };
};
reserved-memory {
--
1.7.1
next prev parent reply other threads:[~2018-10-25 11:13 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-25 11:08 [PATCH 1/6] arm64: dts: Add the status property disable PCIe Xiaowei Bao
2018-10-25 11:08 ` [PATCH 2/6] ARM: dts: ls1021a: " Xiaowei Bao
2018-10-25 11:08 ` [PATCH 3/6] PCI: layerscape: Add the EP mode support Xiaowei Bao
2018-10-25 21:52 ` Rob Herring
2018-10-26 3:45 ` Xiaowei Bao
2018-10-26 7:01 ` Arnd Bergmann
2018-10-26 7:42 ` Xiaowei Bao
2018-10-26 20:28 ` Li Yang
2018-10-29 2:35 ` Xiaowei Bao
2018-10-25 11:08 ` Xiaowei Bao [this message]
2018-10-25 11:09 ` [PATCH 5/6] pci: " Xiaowei Bao
2018-10-26 5:29 ` Kishon Vijay Abraham I
2018-10-26 9:18 ` Xiaowei Bao
2018-10-31 2:33 ` Xiaowei Bao
2018-10-31 4:15 ` Kishon Vijay Abraham I
2018-10-31 10:38 ` Xiaowei Bao
2018-11-05 8:57 ` Kishon Vijay Abraham I
2018-11-05 9:15 ` Xiaowei Bao
2018-11-06 6:06 ` Kishon Vijay Abraham I
2018-11-06 6:48 ` Xiaowei Bao
2018-11-09 2:50 ` Xiaowei Bao
2018-10-25 11:09 ` [PATCH 6/6] misc: pci_endpoint_test: Add the layerscape EP device support Xiaowei Bao
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