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[2003:dc:d717:a100:301a:b549:b11d:5acb]) by smtp.googlemail.com with ESMTPSA id n7-v6sm18987784wrt.60.2018.11.14.14.57.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 14 Nov 2018 14:57:49 -0800 (PST) From: Martin Blumenstingl To: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, jbrunet@baylibre.com, narmstrong@baylibre.com Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, mturquette@baylibre.com, sboyd@kernel.org, Martin Blumenstingl Subject: [RFC v1 0/7] Meson8b: make the CPU clock mutable Date: Wed, 14 Nov 2018 23:57:18 +0100 Message-Id: <20181114225725.2821-1-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.19.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This allows changing the CPU clock on the 32-bit Amlogic Meson SoCs (Meson8, Meson8b and Meson8m2). CPU frequency scaling will be enabled with a separate series by adding the CPU clock and the OPP tables to meson8.dtsi and meson8b.dtsi. While changing the CPU frequency (sys_pll or any of it's post-dividers) we need to run the CPU clock off the XTAL clock. Otherwise the system will lock up because we need to disable the sys_pll to change it's rate. This also makes the clk-pll's .enable hook a no-op if the clock is already enabled. Otherwise we're getting lockups when calling the first clk_{prepare_}enable on the sys_pll or any of it's children (as the CCF propagates the enable event up to the sys_pll). This is because the .enable hook unconditionally disables and enables the clock. However, we can't disable that clock (not even temporarily) if the CPU is running off sys_pll. Additionally this adds support for more M/N combinations in sys_pll to achieve all of the OPPs on Meson8b and all OPPs <= 1608 MHz on Meson8 and Meson8m2. Compared to Amlogic's 3.10 kernel there's one notable difference: we are actually allowing changes to the sys_pll. Amlogic's kernel sets sys_pll to a fixed rate during boot and then uses a timer generate a "virtual clock rate" by toggling between various dividers (for example: sys_pll is set to 1536MHz. to achieve 1008MHz they are toggling every 2500us between 1536MHZ and 768MHz so the average over is 1008MHz). I could reproduce any situation where changing sys_pll failed (for example due to high temperature). To prove that I ran "stress --cpu 4" for multiple hours and then cycled through all available CPU frequencies (while keeping "stress" running in the background). This worked fine on my Meson8b Odroid-C1 and EC-100 boards as well as my Meson8m2 board. Martin Blumenstingl (7): clk: meson: meson8b: run from the XTAL when changing the CPU frequency clk: meson: meson8b: do not use cpu_div3 for cpu_scale_out_sel clk: meson: clk-pll: check if the clock is already enabled clk: meson: clk-pll: add the is_enabled function in the clk_ops clk: meson: meson8b: mark the CPU clock as CLK_IS_CRITICAL clk: meson: meson8b: add support for more M/N values in sys_pll clk: meson: meson8b: allow changing the CPU clock tree drivers/clk/meson/clk-pll.c | 23 +++++++++ drivers/clk/meson/meson8b.c | 94 +++++++++++++++++++++++++++++++++---- 2 files changed, 108 insertions(+), 9 deletions(-) -- 2.19.1