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From: Andi Kleen <ak@linux.intel.com>
To: Kyle Huey <me@kylehuey.com>
Cc: Kan Liang <kan.liang@linux.intel.com>,
	"Peter Zijlstra (Intel)" <peterz@infradead.org>,
	Ingo Molnar <mingo@kernel.org>,
	Robert O'Callahan <robert@ocallahan.org>,
	Alexander Shishkin <alexander.shishkin@linux.intel.com>,
	Arnaldo Carvalho de Melo <acme@redhat.com>,
	Jiri Olsa <jolsa@redhat.com>,
	Linus Torvalds <torvalds@linux-foundation.org>,
	Stephane Eranian <eranian@google.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	Vince Weaver <vincent.weaver@maine.edu>,
	acme@kernel.org, open list <linux-kernel@vger.kernel.org>
Subject: Re: [REGRESSION] x86, perf: counter freezing breaks rr
Date: Tue, 20 Nov 2018 11:41:29 -0800	[thread overview]
Message-ID: <20181120194129.GC13936@tassilo.jf.intel.com> (raw)
In-Reply-To: <CAP045Ap6Mm+r_44YmxNbz6HWtYArg3SAFgzk4Cm_K5HRJaRG7w@mail.gmail.com>

> rr, a userspace record and replay debugger[0], uses the PMU interrupt
> (PMI) to stop a program during replay to inject asynchronous events
> such as signals. With perf counter freezing enabled we are reliably
> seeing perf event overcounts during replay. This behavior is easily

It's hard to see how it could over count since the PMU freezes
earlier than the PMI with freezing. So it should count less.
Did you mean under count?

> Given that we're already at rc3, and that this renders rr unusable,
> we'd ask that counter freezing be disabled for the 4.20 release.

The boot option should be good enough for the release?

A reasonable future option would be to expose an option to disable it in
the perf_event. Then rr could set it.

-Andi

  parent reply	other threads:[~2018-11-20 19:42 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-11-20 16:19 [REGRESSION] x86, perf: counter freezing breaks rr Kyle Huey
2018-11-20 17:08 ` Peter Zijlstra
2018-11-20 17:59   ` [tip:perf/urgent] perf/x86/intel: Fix regression by default disabling perfmon v4 interrupt handling tip-bot for Peter Zijlstra
2018-11-20 18:20   ` [REGRESSION] x86, perf: counter freezing breaks rr Stephane Eranian
2018-11-20 19:50     ` Kyle Huey
2018-11-20 19:41 ` Andi Kleen [this message]
2018-11-20 19:54   ` Kyle Huey
2018-11-20 20:11     ` Andi Kleen
2018-11-20 20:53       ` Kyle Huey
2018-11-20 21:18         ` Andi Kleen
2018-11-20 21:46           ` Kyle Huey
2018-11-20 22:19             ` Andi Kleen
2018-11-20 21:19         ` Stephane Eranian
2018-11-20 21:34           ` Kyle Huey
2018-11-20 22:16       ` Peter Zijlstra
2018-11-20 22:25         ` Peter Zijlstra
2018-11-20 22:38           ` Andi Kleen
2018-11-21  8:14             ` Peter Zijlstra
2018-11-27 22:08               ` Kyle Huey
2018-11-27 23:36                 ` Andi Kleen
2018-11-28  1:25                   ` Stephane Eranian
2018-11-29 14:50                     ` Liang, Kan
2018-11-29 15:35                   ` Peter Zijlstra

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