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[108.119.106.197]) by smtp.gmail.com with ESMTPSA id y28sm698490oix.23.2019.03.15.16.37.48 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 15 Mar 2019 16:37:49 -0700 (PDT) Date: Fri, 15 Mar 2019 18:37:48 -0500 From: Rob Herring To: Lina Iyer Cc: swboyd@chromium.org, evgreen@chromium.org, marc.zyngier@arm.com, linux-kernel@vger.kernel.org, rplsssn@codeaurora.org, linux-arm-msm@vger.kernel.org, thierry.reding@gmail.com, bjorn.andersson@linaro.org, dianders@chromium.org, linus.walleij@linaro.org, devicetree@vger.kernel.org Subject: Re: [PATCH v4 06/10] dt-bindings: sdm845-pinctrl: add wakeup interrupt parent for GPIO Message-ID: <20190315233748.GA7219@bogus> References: <20190313211844.29416-1-ilina@codeaurora.org> <20190313211844.29416-7-ilina@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20190313211844.29416-7-ilina@codeaurora.org> User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Mar 13, 2019 at 03:18:40PM -0600, Lina Iyer wrote: > SDM845 SoC has an always-on interrupt controller (PDC) with select GPIO > routed to the PDC as interrupts that can be used to wake the system up > from deep low power modes and suspend. > > Cc: devicetree@vger.kernel.org > Signed-off-by: Lina Iyer > --- > .../devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt | 7 ++++++- > 1 file changed, 6 insertions(+), 1 deletion(-) I still don't love this being specific to wake-up, but don't have a better suggestion. One nit, otherwise: Reviewed-by: Rob Herring > > diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt > index 665aadb5ea28..f0fedbc5d41a 100644 > --- a/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt > +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt > @@ -29,6 +29,11 @@ SDM845 platform. > Definition: must be 2. Specifying the pin number and flags, as defined > in > > +- wakeup-parent: > + Usage: optional > + Value type: > + Definition: A phandle to the wakeup interrupt controller for the SoC. > + > - gpio-controller: > Usage: required > Value type: > @@ -53,7 +58,6 @@ pin, a group, or a list of pins or groups. This configuration can include the > mux function to select on those pin(s)/group(s), and various pin configuration > parameters, such as pull-up, drive strength, etc. > > - > PIN CONFIGURATION NODES: > > The name of each subnode is not important; all subnodes should be enumerated > @@ -160,6 +164,7 @@ Example: > #gpio-cells = <2>; > interrupt-controller; > #interrupt-cells = <2>; > + wake-parent = <&pdc_intc>; wakeup-parent > > qup9_active: qup9-active { > mux { > -- > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, > a Linux Foundation Collaborative Project >