From: Weiyi Lu <weiyi.lu@mediatek.com>
To: Nicolas Boichat <drinkcat@chromium.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
Rob Herring <robh@kernel.org>
Cc: James Liao <jamesjj.liao@mediatek.com>,
Fan Chen <fan.chen@mediatek.com>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>,
<linux-mediatek@lists.infradead.org>,
<srv_heupstream@mediatek.com>, Weiyi Lu <weiyi.lu@mediatek.com>
Subject: [PATCH v5 02/14] dt-bindings: soc: Add MT8183 power dt-bindings
Date: Tue, 19 Mar 2019 16:01:28 +0800 [thread overview]
Message-ID: <20190319080140.24055-3-weiyi.lu@mediatek.com> (raw)
In-Reply-To: <20190319080140.24055-1-weiyi.lu@mediatek.com>
Add power dt-bindings of MT8183 and introduces "BASIC" and
"SUBSYS" clock types in binding document.
The "BASIC" type is compatible to the original power control with
clock name [a-z]+[0-9]*, e.g. mm, vpu1.
The "SUBSYS" type is used for bus protection control with clock
name [a-z]+-[0-9]+, e.g. isp-0, cam-1.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
.../bindings/soc/mediatek/scpsys.txt | 14 ++++++++++
include/dt-bindings/power/mt8183-power.h | 26 +++++++++++++++++++
2 files changed, 40 insertions(+)
create mode 100644 include/dt-bindings/power/mt8183-power.h
diff --git a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
index d6fe16f094af..b4728ce81c43 100644
--- a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
+++ b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
@@ -14,6 +14,7 @@ power/power_domain.txt. It provides the power domains defined in
- include/dt-bindings/power/mt2701-power.h
- include/dt-bindings/power/mt2712-power.h
- include/dt-bindings/power/mt7622-power.h
+- include/dt-bindings/power/mt8183-power.h
Required properties:
- compatible: Should be one of:
@@ -24,18 +25,31 @@ Required properties:
- "mediatek,mt7623-scpsys", "mediatek,mt2701-scpsys": For MT7623 SoC
- "mediatek,mt7623a-scpsys": For MT7623A SoC
- "mediatek,mt8173-scpsys"
+ - "mediatek,mt8183-scpsys"
- #power-domain-cells: Must be 1
- reg: Address range of the SCPSYS unit
- infracfg: must contain a phandle to the infracfg controller
- clock, clock-names: clocks according to the common clock binding.
These are clocks which hardware needs to be
enabled before enabling certain power domains.
+ The new clock type "BASIC" belongs to the type above.
+ As to the new clock type "SUBSYS" needs to be
+ enabled before releasing bus protection.
Required clocks for MT2701 or MT7623: "mm", "mfg", "ethif"
Required clocks for MT2712: "mm", "mfg", "venc", "jpgdec", "audio", "vdec"
Required clocks for MT6797: "mm", "mfg", "vdec"
Required clocks for MT7622: "hif_sel"
Required clocks for MT7622A: "ethif"
Required clocks for MT8173: "mm", "mfg", "venc", "venc_lt"
+ Required clocks for MT8183: BASIC: "audio", "mfg", "mm", "cam", "isp",
+ "vpu", "vpu1", "vpu2", "vpu3"
+ SUBSYS: "mm-0", "mm-1", "mm-2", "mm-3",
+ "mm-4", "mm-5", "mm-6", "mm-7",
+ "mm-8", "mm-9", "isp-0", "isp-1",
+ "cam-0", "cam-1", "cam-2", "cam-3",
+ "cam-4", "cam-5", "cam-6", "vpu-0",
+ "vpu-1", "vpu-2", "vpu-3", "vpu-4",
+ "vpu-5"
Optional properties:
- vdec-supply: Power supply for the vdec power domain
diff --git a/include/dt-bindings/power/mt8183-power.h b/include/dt-bindings/power/mt8183-power.h
new file mode 100644
index 000000000000..5c0c8c7e3cd0
--- /dev/null
+++ b/include/dt-bindings/power/mt8183-power.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (c) 2018 MediaTek Inc.
+ * Author: Weiyi Lu <weiyi.lu@mediatek.com>
+ */
+
+#ifndef _DT_BINDINGS_POWER_MT8183_POWER_H
+#define _DT_BINDINGS_POWER_MT8183_POWER_H
+
+#define MT8183_POWER_DOMAIN_AUDIO 0
+#define MT8183_POWER_DOMAIN_CONN 1
+#define MT8183_POWER_DOMAIN_MFG_ASYNC 2
+#define MT8183_POWER_DOMAIN_MFG 3
+#define MT8183_POWER_DOMAIN_MFG_CORE0 4
+#define MT8183_POWER_DOMAIN_MFG_CORE1 5
+#define MT8183_POWER_DOMAIN_MFG_2D 6
+#define MT8183_POWER_DOMAIN_DISP 7
+#define MT8183_POWER_DOMAIN_CAM 8
+#define MT8183_POWER_DOMAIN_ISP 9
+#define MT8183_POWER_DOMAIN_VDEC 10
+#define MT8183_POWER_DOMAIN_VENC 11
+#define MT8183_POWER_DOMAIN_VPU_TOP 12
+#define MT8183_POWER_DOMAIN_VPU_CORE0 13
+#define MT8183_POWER_DOMAIN_VPU_CORE1 14
+
+#endif /* _DT_BINDINGS_POWER_MT8183_POWER_H */
--
2.18.0
next prev parent reply other threads:[~2019-03-19 8:03 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-19 8:01 [PATCH v5 00/14] Mediatek MT8183 scpsys support Weiyi Lu
2019-03-19 8:01 ` [PATCH v5 01/14] dt-bindings: mediatek: Add property to mt8183 smi-common Weiyi Lu
2019-03-19 8:01 ` Weiyi Lu [this message]
2019-03-19 8:01 ` [PATCH v5 03/14] soc: mediatek: Switch to SPDX license identifier Weiyi Lu
2019-03-19 8:01 ` [PATCH v5 04/14] soc: mediatek: Refactor polling timeout and documentation Weiyi Lu
2019-03-19 11:45 ` Nicolas Boichat
2019-06-19 9:11 ` Weiyi Lu
2019-03-19 8:01 ` [PATCH v5 05/14] soc: mediatek: Refactor regulator control Weiyi Lu
2019-03-19 8:01 ` [PATCH v5 06/14] soc: mediatek: Refactor clock control Weiyi Lu
2019-03-19 12:02 ` Nicolas Boichat
2019-06-19 9:19 ` Weiyi Lu
2019-03-19 8:01 ` [PATCH v5 07/14] soc: mediatek: Refactor sram control Weiyi Lu
2019-03-19 12:07 ` Nicolas Boichat
2019-06-19 9:30 ` Weiyi Lu
2019-03-19 8:01 ` [PATCH v5 08/14] soc: mediatek: Refactor bus protection control Weiyi Lu
2019-03-19 12:09 ` Nicolas Boichat
2019-06-19 9:31 ` Weiyi Lu
2019-03-19 8:01 ` [PATCH v5 09/14] soc: mediatek: Add basic_clk_name to scp_power_data Weiyi Lu
2019-03-21 6:02 ` Nicolas Boichat
2019-06-19 9:36 ` Weiyi Lu
2019-03-19 8:01 ` [PATCH v5 10/14] soc: mediatek: Add multiple step bus protection control Weiyi Lu
2019-03-21 5:57 ` Nicolas Boichat
2019-06-19 9:43 ` Weiyi Lu
2019-03-19 8:01 ` [PATCH v5 11/14] soc: mediatek: Add subsys clock control for bus protection Weiyi Lu
2019-03-19 8:01 ` [PATCH v5 12/14] soc: mediatek: Add extra sram control Weiyi Lu
2019-03-19 8:01 ` [PATCH v5 13/14] soc: mediatek: Add MT8183 scpsys support Weiyi Lu
2019-03-19 8:01 ` [PATCH v5 14/14] arm64: dts: Add power controller device node of MT8183 Weiyi Lu
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