From: Andy Shevchenko <andriy.shevchenko@intel.com>
To: Rahul Tanwar <rahul.tanwar@linux.intel.com>
Cc: linux-serial@vger.kernel.org, devicetree@vger.kernel.org,
gregkh@linuxfoundation.org, linux-kernel@vger.kernel.org,
jslaby@suse.com, robh+dt@kernel.org, mark.rutland@arm.com,
qi-ming.wu@intel.com, cheol.yong.kim@intel.com,
rahul.tanwar@intel.com
Subject: Re: [PATCH 4/5] dt-bindings: serial: lantiq: Update for new SoC
Date: Wed, 7 Aug 2019 16:17:42 +0300 [thread overview]
Message-ID: <20190807131742.GV30120@smile.fi.intel.com> (raw)
In-Reply-To: <47c6565f5537575b16f65ca5ccc5ecfc61818dbc.1565160764.git.rahul.tanwar@linux.intel.com>
On Wed, Aug 07, 2019 at 05:21:34PM +0800, Rahul Tanwar wrote:
> There is a new Intel Atom based Lightning Mountain(LGM) network processor SoC which
> reuses Lantiq ASC serial controller IP. This patch adds new compatible string
> and its expected property value in order to support the driver for LGM as well.
I think it makes sense to convert to YAML before adding new properties.
>
> Signed-off-by: Rahul Tanwar <rahul.tanwar@linux.intel.com>
> ---
> Documentation/devicetree/bindings/serial/lantiq_asc.txt | 17 +++++++++++++++--
> 1 file changed, 15 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/serial/lantiq_asc.txt b/Documentation/devicetree/bindings/serial/lantiq_asc.txt
> index 40e81a5818f6..18b45dd13a61 100644
> --- a/Documentation/devicetree/bindings/serial/lantiq_asc.txt
> +++ b/Documentation/devicetree/bindings/serial/lantiq_asc.txt
> @@ -1,10 +1,14 @@
> Lantiq SoC ASC serial controller
>
> Required properties:
> -- compatible : Should be "lantiq,asc"
> +- compatible : Should be "lantiq,asc" or "intel,lgm-asc"
> - reg : Address and length of the register set for the device
> -- interrupts: the 3 (tx rx err) interrupt numbers. The interrupt specifier
> +- interrupts:
> + For "lantiq,asc" - the 3 (tx rx err) interrupt numbers. The interrupt specifier
> depends on the interrupt-parent interrupt controller.
> + or
> + For "intel,lgm-asc" - the common interrupt number for all of tx rx & err interrupts
> + followed by level/sense specifier.
>
> Optional properties:
> - clocks: Should contain frequency clock and gate clock
> @@ -29,3 +33,12 @@ asc1: serial@e100c00 {
> interrupt-parent = <&icu0>;
> interrupts = <112 113 114>;
> };
> +
> +asc0: serial@e0a00000 {
> + compatible = "intel,lgm-asc";
> + reg = <0xe0a00000 0x1000>;
> + interrupt-parent = <&ioapic1>;
> + interrupts = <128 1>;
> + clocks = <&cgu0 LGM_CLK_NOC4>, <&cgu0 LGM_GCLK_ASC0>;
> + clock-names = "freq", "asc";
> +};
> --
> 2.11.0
>
--
With Best Regards,
Andy Shevchenko
next parent reply other threads:[~2019-08-07 13:17 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <cover.1565160764.git.rahul.tanwar@linux.intel.com>
[not found] ` <47c6565f5537575b16f65ca5ccc5ecfc61818dbc.1565160764.git.rahul.tanwar@linux.intel.com>
2019-08-07 13:17 ` Andy Shevchenko [this message]
[not found] ` <7912786cccad60c72b20ea724af1def505ab22aa.1565160764.git.rahul.tanwar@linux.intel.com>
2019-08-07 13:19 ` [PATCH 1/5] serial: lantiq: Add SMP support Andy Shevchenko
[not found] ` <12c3029f406ca1fedf14154154f7082e358f0473.1565160764.git.rahul.tanwar@linux.intel.com>
2019-08-07 13:20 ` [PATCH 2/5] serial: lantiq: Use proper DT compatible string Andy Shevchenko
[not found] ` <6dd57ea99f734bd4e413f6913914c0a93c00f295.1565160764.git.rahul.tanwar@linux.intel.com>
2019-08-07 13:29 ` [PATCH 3/5] serial: lantiq: Make IRQ & ISR assignment dynamic Andy Shevchenko
[not found] ` <a947355d6cf0ab71205e81779e1549f42f3f945a.1565160764.git.rahul.tanwar@linux.intel.com>
2019-08-07 13:31 ` [PATCH 5/5] serial: lantiq: Add support for Lightning Mountain SoC Andy Shevchenko
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20190807131742.GV30120@smile.fi.intel.com \
--to=andriy.shevchenko@intel.com \
--cc=cheol.yong.kim@intel.com \
--cc=devicetree@vger.kernel.org \
--cc=gregkh@linuxfoundation.org \
--cc=jslaby@suse.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-serial@vger.kernel.org \
--cc=mark.rutland@arm.com \
--cc=qi-ming.wu@intel.com \
--cc=rahul.tanwar@intel.com \
--cc=rahul.tanwar@linux.intel.com \
--cc=robh+dt@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).