From: Peter Zijlstra <peterz@infradead.org>
To: Leo Yan <leo.yan@linaro.org>
Cc: Will Deacon <will@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Mike Leach <mike.leach@linaro.org>,
Adrian Hunter <adrian.hunter@intel.com>,
Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
"H . Peter Anvin" <hpa@zytor.com>,
x86@kernel.org,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Mathieu Poirier <mathieu.poirier@linaro.org>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Jiri Olsa <jolsa@redhat.com>,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH RFC 1/6] perf/x86: Add perf text poke event
Date: Fri, 1 Nov 2019 11:09:03 +0100 [thread overview]
Message-ID: <20191101100903.GI5671@hirez.programming.kicks-ass.net> (raw)
In-Reply-To: <20191101100440.GU4131@hirez.programming.kicks-ass.net>
On Fri, Nov 01, 2019 at 11:04:40AM +0100, Peter Zijlstra wrote:
> I'm thinking something along the lines of:
>
> static uintptr_t nosync_addr;
> static u32 nosync_insn;
>
> int __kprobes aarch64_insn_patch_text_nosync(void *addr, u32 insn)
> {
> const u32 break = // some_breakpoint_insn;
> uintptr_t tp = (uintptr_t)addr;
> int ret;
>
> lockdep_assert_held(&text_mutex);
>
> /* A64 instructions must be word aligned */
> if (tp & 0x3)
> return -EINVAL;
>
> if (perf_text_poke_update_enabled()) {
>
> nosync_insn = insn;
> smp_store_release(&nosync_addr, tp);
>
> ret = aarch64_insn_write(addr, break);
> if (ret == 0)
> __flush_icache_range(tp, tp + AARCH64_INSN_SIZE);
>
> perf_event_text_poke(....);
> }
>
> ret = aarch64_insn_write(addr, insn);
> if (ret == 0)
> __flush_icache_range(tp, tp + AARCH64_INSN_SIZE);
// barrier that guarantees iflush completion ? dsb(osh) ?
WRITE_ONCE(nosync_addr, NULL);
> return ret;
> }
>
> And have the 'break' handler do:
>
> aarch64_insn_break_handler(struct pt_regs *regs)
> {
> unsigned long addr = smp_load_acquire(&nosync_addr);
> u32 insn = nosync_insn;
>
> if (regs->ip != addr)
> return;
>
> // emulate @insn
> }
>
> I understood from Will the whole nosync scheme only works for a limited
> set of instructions, but you only have to implement emulation for the
> actual instructions used of course.
>
> (which is what we do on x86)
>
> Does this sound workable?
next prev parent reply other threads:[~2019-11-01 10:09 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-25 12:59 [PATCH RFC 0/6] perf/x86: Add perf text poke event Adrian Hunter
2019-10-25 12:59 ` [PATCH RFC 1/6] " Adrian Hunter
2019-10-30 10:47 ` Leo Yan
2019-10-30 12:46 ` Peter Zijlstra
2019-10-30 14:19 ` Leo Yan
2019-10-30 15:00 ` Mike Leach
2019-10-30 16:23 ` Peter Zijlstra
2019-10-31 7:31 ` Leo Yan
2019-11-01 10:04 ` Peter Zijlstra
2019-11-01 10:09 ` Peter Zijlstra [this message]
2019-11-04 2:23 ` Leo Yan
2019-11-08 15:05 ` Leo Yan
2019-11-11 14:46 ` Peter Zijlstra
2019-11-11 15:39 ` Will Deacon
2019-11-11 16:05 ` Peter Zijlstra
2019-11-11 17:29 ` Will Deacon
2019-11-11 20:32 ` Peter Zijlstra
[not found] ` <CAJ9a7VgZH7g=rFDpKf=FzEcyBVLS_WjqbrqtRnjOi7WOY4st+w@mail.gmail.com>
2019-11-01 10:06 ` Peter Zijlstra
2019-11-04 10:40 ` Peter Zijlstra
2019-11-04 12:32 ` Adrian Hunter
2019-10-25 12:59 ` [PATCH RFC 2/6] perf dso: Refactor dso_cache__read() Adrian Hunter
2019-10-25 14:54 ` Arnaldo Carvalho de Melo
2019-10-28 15:39 ` Jiri Olsa
2019-10-29 9:19 ` Adrian Hunter
2019-11-12 11:18 ` [tip: perf/core] " tip-bot2 for Adrian Hunter
2019-10-25 12:59 ` [PATCH RFC 3/6] perf dso: Add dso__data_write_cache_addr() Adrian Hunter
2019-10-28 15:45 ` Jiri Olsa
2019-10-29 9:20 ` Adrian Hunter
2019-11-12 11:18 ` [tip: perf/core] " tip-bot2 for Adrian Hunter
2019-10-25 12:59 ` [PATCH RFC 4/6] perf tools: Add support for PERF_RECORD_TEXT_POKE Adrian Hunter
2019-10-25 12:59 ` [PATCH RFC 5/6] perf auxtrace: Add auxtrace_cache__remove() Adrian Hunter
2019-10-25 14:48 ` Arnaldo Carvalho de Melo
2019-11-12 11:18 ` [tip: perf/core] " tip-bot2 for Adrian Hunter
2019-10-25 13:00 ` [PATCH RFC 6/6] perf intel-pt: Add support for text poke events Adrian Hunter
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