From: Dmitry Osipenko <digetx@gmail.com>
To: Thierry Reding <thierry.reding@gmail.com>,
Jonathan Hunter <jonathanh@nvidia.com>,
Peter De Schrijver <pdeschrijver@nvidia.com>,
Prashant Gaikwad <pgaikwad@nvidia.com>,
"Rafael J. Wysocki" <rjw@rjwysocki.net>,
Viresh Kumar <viresh.kumar@linaro.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Peter Geis <pgwipeout@gmail.com>,
Nicolas Chauvet <kwizart@gmail.com>,
Marcel Ziswiler <marcel.ziswiler@toradex.com>
Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org,
linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH v5 03/11] clk: tegra: cclk: Add helpers for handling PLLX rate changes
Date: Mon, 18 Nov 2019 19:45:04 +0300 [thread overview]
Message-ID: <20191118164512.8676-4-digetx@gmail.com> (raw)
In-Reply-To: <20191118164512.8676-1-digetx@gmail.com>
CCLK should be re-parented away from PLLX if PLLX's rate is changing.
The PLLP parent is a common safe CPU parent for all Tegra SoCs, thus
CCLK will be re-parented to PLLP before PLLX rate-change begins and then
switched back to PLLX after the rate-change completion. This patch adds
helper functions which perform CCLK re-parenting, these helpers will be
utilized by further patches.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
drivers/clk/tegra/clk-tegra-super-cclk.c | 34 ++++++++++++++++++++++++
drivers/clk/tegra/clk.h | 2 ++
2 files changed, 36 insertions(+)
diff --git a/drivers/clk/tegra/clk-tegra-super-cclk.c b/drivers/clk/tegra/clk-tegra-super-cclk.c
index 7bcb9e8d0860..a03119c30456 100644
--- a/drivers/clk/tegra/clk-tegra-super-cclk.c
+++ b/drivers/clk/tegra/clk-tegra-super-cclk.c
@@ -25,6 +25,9 @@
#define SUPER_CDIV_ENB BIT(31)
+static struct tegra_clk_super_mux *cclk_super;
+static bool cclk_on_pllx;
+
static u8 cclk_super_get_parent(struct clk_hw *hw)
{
return tegra_clk_super_ops.get_parent(hw);
@@ -115,6 +118,9 @@ struct clk *tegra_clk_register_super_cclk(const char *name,
struct clk_init_data init;
u32 val;
+ if (WARN_ON(cclk_super))
+ return ERR_PTR(-EBUSY);
+
super = kzalloc(sizeof(*super), GFP_KERNEL);
if (!super)
return ERR_PTR(-ENOMEM);
@@ -173,6 +179,34 @@ struct clk *tegra_clk_register_super_cclk(const char *name,
clk = clk_register(NULL, &super->hw);
if (IS_ERR(clk))
kfree(super);
+ else
+ cclk_super = super;
return clk;
}
+
+int tegra_cclk_pre_pllx_rate_change(void)
+{
+ if (IS_ERR_OR_NULL(cclk_super))
+ return -EINVAL;
+
+ if (cclk_super_get_parent(&cclk_super->hw) == PLLX_INDEX)
+ cclk_on_pllx = true;
+ else
+ cclk_on_pllx = false;
+
+ /*
+ * CPU needs to be temporarily re-parented away from PLLX if PLLX
+ * changes its rate. PLLP is a safe parent for CPU on all Tegra SoCs.
+ */
+ if (cclk_on_pllx)
+ cclk_super_set_parent(&cclk_super->hw, PLLP_INDEX);
+
+ return 0;
+}
+
+void tegra_cclk_post_pllx_rate_change(void)
+{
+ if (cclk_on_pllx)
+ cclk_super_set_parent(&cclk_super->hw, PLLX_INDEX);
+}
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index fa18bef914af..0afe28f4372b 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -771,6 +771,8 @@ struct clk *tegra_clk_register_super_cclk(const char *name,
const char * const *parent_names, u8 num_parents,
unsigned long flags, void __iomem *reg, u8 clk_super_flags,
spinlock_t *lock);
+int tegra_cclk_pre_pllx_rate_change(void);
+void tegra_cclk_post_pllx_rate_change(void);
/**
* struct tegra_sdmmc_mux - switch divider with Low Jitter inputs for SDMMC
--
2.23.0
next prev parent reply other threads:[~2019-11-18 16:47 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-18 16:45 [PATCH v5 00/11] NVIDIA Tegra20 CPUFreq driver major update Dmitry Osipenko
2019-11-18 16:45 ` [PATCH v5 01/11] clk: tegra: Add custom CCLK implementation Dmitry Osipenko
2019-11-18 16:45 ` [PATCH v5 02/11] clk: tegra: pll: Add pre/post rate-change hooks Dmitry Osipenko
2019-11-18 16:45 ` Dmitry Osipenko [this message]
2019-11-18 16:45 ` [PATCH v5 04/11] clk: tegra20: Use custom CCLK implementation Dmitry Osipenko
2019-11-18 16:45 ` [PATCH v5 05/11] clk: tegra30: " Dmitry Osipenko
2019-11-18 16:45 ` [PATCH v5 06/11] dt-bindings: cpufreq: Add binding for NVIDIA Tegra20/30 Dmitry Osipenko
2019-11-18 16:45 ` [PATCH v5 07/11] cpufreq: dt-platdev: Blacklist NVIDIA Tegra20 and Tegra30 SoCs Dmitry Osipenko
2019-11-18 16:51 ` Dmitry Osipenko
2019-12-13 13:27 ` Dmitry Osipenko
2019-12-16 4:05 ` Viresh Kumar
2019-12-16 4:08 ` Viresh Kumar
2019-12-16 14:11 ` Dmitry Osipenko
2019-11-18 16:45 ` [PATCH v5 08/11] cpufreq: tegra20: Use generic cpufreq-dt driver (Tegra30 supported now) Dmitry Osipenko
2019-11-18 16:45 ` [PATCH v5 09/11] ARM: tegra: Create tegra20-cpufreq platform device on Tegra30 Dmitry Osipenko
2019-11-18 16:45 ` [PATCH v5 10/11] ARM: dts: tegra30: beaver: Set up voltage regulators for DVFS Dmitry Osipenko
2019-11-18 16:45 ` [PATCH v5 11/11] ARM: dts: tegra30: beaver: Add CPU Operating Performance Points Dmitry Osipenko
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