From: Andrew Murray <andrew.murray@arm.com>
To: Kishon Vijay Abraham I <kishon@ti.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Rob Herring <robh+dt@kernel.org>, Arnd Bergmann <arnd@arndb.de>,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org
Subject: Re: [PATCH 06/13] PCI: cadence: Allow pci_host_bridge to have custom pci_ops
Date: Tue, 17 Dec 2019 12:32:44 +0000 [thread overview]
Message-ID: <20191217123243.GC24359@e119886-lin.cambridge.arm.com> (raw)
In-Reply-To: <20191209092147.22901-7-kishon@ti.com>
On Mon, Dec 09, 2019 at 02:51:40PM +0530, Kishon Vijay Abraham I wrote:
> Certain platforms like TI's J721E allows only 32-bit configuration
> space access. In such cases pci_generic_config_read and
> pci_generic_config_write cannot be used. Add support in Cadence core
> to let pci_host_bridge have custom pci_ops.
>
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---
> drivers/pci/controller/cadence/pcie-cadence-host.c | 7 ++++---
> drivers/pci/controller/cadence/pcie-cadence.h | 8 ++++++++
> 2 files changed, 12 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c
> index 0929554f5a81..2efc33b1cade 100644
> --- a/drivers/pci/controller/cadence/pcie-cadence-host.c
> +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c
> @@ -12,8 +12,8 @@
>
> #include "pcie-cadence.h"
>
> -static void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn,
> - int where)
> +void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn,
> + int where)
> {
> struct pci_host_bridge *bridge = pci_find_host_bridge(bus);
> struct cdns_pcie_rc *rc = pci_host_bridge_priv(bridge);
> @@ -289,7 +289,8 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc)
> list_splice_init(&resources, &bridge->windows);
> bridge->dev.parent = dev;
> bridge->busnr = pcie->bus;
> - bridge->ops = &cdns_pcie_host_ops;
> + if (!bridge->ops)
> + bridge->ops = &cdns_pcie_host_ops;
> bridge->map_irq = of_irq_parse_and_map_pci;
> bridge->swizzle_irq = pci_common_swizzle;
>
> diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h
> index 5171d0da37da..c879dd3d2893 100644
> --- a/drivers/pci/controller/cadence/pcie-cadence.h
> +++ b/drivers/pci/controller/cadence/pcie-cadence.h
> @@ -472,11 +472,19 @@ static inline bool cdns_pcie_is_link_up(struct cdns_pcie *pcie)
>
> #ifdef CONFIG_PCIE_CADENCE_HOST
> int cdns_pcie_host_setup(struct cdns_pcie_rc *rc);
> +void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn,
> + int where);
The commit message doesn't explain why this change in visibility is needed).
> #else
> static inline int cdns_pcie_host_setup(struct cdns_pcie_rc *rc)
> {
> return 0;
> }
> +
> +static inline void __iomem *cdns_pci_map_bus(struct pci_bus *bus,
> + unsigned int devfn,
> + int where)
> +{
This still needs to return something right?
Thanks,
Andrew Murray
> +}
> #endif
>
> #ifdef CONFIG_PCIE_CADENCE_EP
> --
> 2.17.1
>
next prev parent reply other threads:[~2019-12-17 12:32 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-09 9:21 [PATCH 00/13] Add PCIe support to TI's J721E SoC Kishon Vijay Abraham I
2019-12-09 9:21 ` [PATCH 01/13] PCI: cadence: Remove stray "pm_runtime_put_sync()" in error path Kishon Vijay Abraham I
2019-12-16 13:45 ` Andrew Murray
2019-12-19 8:31 ` Kishon Vijay Abraham I
2019-12-09 9:21 ` [PATCH 02/13] linux/kernel.h: Add PTR_ALIGN_DOWN macro Kishon Vijay Abraham I
2019-12-09 9:21 ` [PATCH 03/13] PCI: cadence: Add support to use custom read and write accessors Kishon Vijay Abraham I
2019-12-16 14:07 ` Andrew Murray
2019-12-19 11:41 ` Kishon Vijay Abraham I
2019-12-09 9:21 ` [PATCH 04/13] PCI: cadence: Add support to start link and verify link status Kishon Vijay Abraham I
2019-12-17 11:58 ` Andrew Murray
2019-12-19 12:01 ` Kishon Vijay Abraham I
2019-12-09 9:21 ` [PATCH 05/13] PCI: cadence: Add read and write accessors to perform only 32-bit accesses Kishon Vijay Abraham I
2019-12-09 21:15 ` Bjorn Helgaas
2019-12-16 14:49 ` Andrew Murray
2019-12-19 11:56 ` Kishon Vijay Abraham I
2019-12-19 12:03 ` Arnd Bergmann
2019-12-19 13:19 ` Kishon Vijay Abraham I
2019-12-19 20:16 ` Arnd Bergmann
2019-12-17 23:36 ` Bjorn Helgaas
2019-12-19 12:49 ` Kishon Vijay Abraham I
2019-12-09 9:21 ` [PATCH 06/13] PCI: cadence: Allow pci_host_bridge to have custom pci_ops Kishon Vijay Abraham I
2019-12-17 12:32 ` Andrew Murray [this message]
2019-12-19 12:02 ` Kishon Vijay Abraham I
2019-12-09 9:21 ` [PATCH 07/13] PCI: cadence: Add new *ops* for CPU addr fixup Kishon Vijay Abraham I
2019-12-17 12:40 ` Andrew Murray
2019-12-19 12:03 ` Kishon Vijay Abraham I
2019-12-09 9:21 ` [PATCH 08/13] PCI: cadence: Use local management register to configure Vendor ID Kishon Vijay Abraham I
2019-12-17 12:42 ` Andrew Murray
2019-12-19 12:12 ` Kishon Vijay Abraham I
2019-12-09 9:21 ` [PATCH 09/13] dt-bindings: PCI: Add host mode dt-bindings for TI's J721E SoC Kishon Vijay Abraham I
2019-12-19 0:08 ` Rob Herring
2019-12-19 13:13 ` Kishon Vijay Abraham I
2019-12-24 8:06 ` Kishon Vijay Abraham I
2019-12-09 9:21 ` [PATCH 10/13] dt-bindings: PCI: Add EP " Kishon Vijay Abraham I
2019-12-19 0:14 ` Rob Herring
2019-12-19 13:14 ` Kishon Vijay Abraham I
2019-12-09 9:21 ` [PATCH 11/13] PCI: j721e: Add TI J721E PCIe driver Kishon Vijay Abraham I
2019-12-17 14:23 ` Andrew Murray
2019-12-19 22:47 ` Bjorn Helgaas
2019-12-09 9:21 ` [PATCH 12/13] misc: pci_endpoint_test: Add J721E in pci_device_id table Kishon Vijay Abraham I
2019-12-09 9:21 ` [PATCH 13/13] MAINTAINERS: Add Kishon Vijay Abraham I for TI J721E SoC PCIe Kishon Vijay Abraham I
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20191217123243.GC24359@e119886-lin.cambridge.arm.com \
--to=andrew.murray@arm.com \
--cc=arnd@arndb.de \
--cc=bhelgaas@google.com \
--cc=devicetree@vger.kernel.org \
--cc=kishon@ti.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-omap@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=lorenzo.pieralisi@arm.com \
--cc=robh+dt@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).