From: Vinod Koul <vkoul@kernel.org>
To: Stephen Boyd <sboyd@kernel.org>
Cc: linux-arm-msm@vger.kernel.org,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Taniya Das <tdas@codeaurora.org>,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
devicetree@vger.kernel.org, Andy Gross <agross@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
psodagud@codeaurora.org, tsoni@codeaurora.org,
jshriram@codeaurora.org, vnkgutta@codeaurora.org,
Vinod Koul <vkoul@kernel.org>
Subject: [PATCH v4 2/5] clk: qcom: clk-alpha-pll: Refactor trion PLL
Date: Mon, 24 Feb 2020 10:20:00 +0530 [thread overview]
Message-ID: <20200224045003.3783838-3-vkoul@kernel.org> (raw)
In-Reply-To: <20200224045003.3783838-1-vkoul@kernel.org>
From: Taniya Das <tdas@codeaurora.org>
Remove duplicate function for calculating the round rate of PLL and also
update the trion pll ops to use the common function.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
drivers/clk/qcom/clk-alpha-pll.c | 33 ++++++--------------------------
1 file changed, 6 insertions(+), 27 deletions(-)
diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index 0bdf6e45fac9..0adec585eb4f 100644
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -845,33 +845,12 @@ static unsigned long
clk_trion_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
{
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
- struct regmap *regmap = pll->clkr.regmap;
- u32 l, frac;
- u64 prate = parent_rate;
-
- regmap_read(regmap, PLL_L_VAL(pll), &l);
- regmap_read(regmap, PLL_ALPHA_VAL(pll), &frac);
-
- return alpha_pll_calc_rate(prate, l, frac, ALPHA_REG_16BIT_WIDTH);
-}
-
-static long clk_trion_pll_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *prate)
-{
- struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
- unsigned long min_freq, max_freq;
- u32 l;
- u64 a;
-
- rate = alpha_pll_round_rate(rate, *prate,
- &l, &a, ALPHA_REG_16BIT_WIDTH);
- if (!pll->vco_table || alpha_pll_find_vco(pll, rate))
- return rate;
+ u32 l, frac, alpha_width = pll_alpha_width(pll);
- min_freq = pll->vco_table[0].min_freq;
- max_freq = pll->vco_table[pll->num_vco - 1].max_freq;
+ regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
+ regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &frac);
- return clamp(rate, min_freq, max_freq);
+ return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width);
}
const struct clk_ops clk_alpha_pll_fixed_ops = {
@@ -917,7 +896,7 @@ const struct clk_ops clk_trion_fixed_pll_ops = {
.disable = clk_trion_pll_disable,
.is_enabled = clk_trion_pll_is_enabled,
.recalc_rate = clk_trion_pll_recalc_rate,
- .round_rate = clk_trion_pll_round_rate,
+ .round_rate = clk_alpha_pll_round_rate,
};
EXPORT_SYMBOL_GPL(clk_trion_fixed_pll_ops);
@@ -1173,7 +1152,7 @@ static int alpha_pll_fabia_set_rate(struct clk_hw *hw, unsigned long rate,
* Due to limited number of bits for fractional rate programming, the
* rounded up rate could be marginally higher than the requested rate.
*/
- if (rrate > max || rrate < rate) {
+ if (rrate > (rate + PLL_RATE_MARGIN) || rrate < rate) {
pr_err("%s: Rounded rate %lu not within range [%lu, %lu)\n",
clk_hw_get_name(hw), rrate, rate, max);
return -EINVAL;
--
2.24.1
next prev parent reply other threads:[~2020-02-24 4:50 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-24 4:49 [PATCH v4 0/5] Add clock drivers for SM8250 SoC Vinod Koul
2020-02-24 4:49 ` [PATCH v4 1/5] clk: qcom: clk-alpha-pll: Use common names for defines Vinod Koul
2020-03-09 22:20 ` Stephen Boyd
2020-02-24 4:50 ` Vinod Koul [this message]
2020-03-09 22:21 ` [PATCH v4 2/5] clk: qcom: clk-alpha-pll: Refactor trion PLL Stephen Boyd
2020-02-24 4:50 ` [PATCH v4 3/5] clk: qcom: clk-alpha-pll: Add support for controlling Lucid PLLs Vinod Koul
2020-03-09 22:21 ` Stephen Boyd
2020-02-24 4:50 ` [PATCH v4 4/5] dt-bindings: clock: Add SM8250 GCC clock bindings Vinod Koul
2020-02-25 17:05 ` Rob Herring
2020-03-09 22:21 ` Stephen Boyd
2020-02-24 4:50 ` [PATCH v4 5/5] clk: qcom: gcc: Add global clock controller driver for SM8250 Vinod Koul
2020-03-09 22:21 ` Stephen Boyd
2020-02-26 14:09 ` [PATCH v4 0/5] Add clock drivers for SM8250 SoC Bryan O'Donoghue
2020-02-26 14:11 ` Bryan O'Donoghue
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