Re: [PATCH v8 00/11] arm64: Branch Target Identification support

From: Mark Brown <broonie@kernel.org>
To: Catalin Marinas <catalin.marinas@arm.com>
Cc: "Will Deacon" <will@kernel.org>,
	"Alexander Viro" <viro@zeniv.linux.org.uk>,
	"Paul Elliott" <paul.elliott@arm.com>,
	"Peter Zijlstra" <peterz@infradead.org>,
	"Yu-cheng Yu" <yu-cheng.yu@intel.com>,
	"Amit Kachhap" <amit.kachhap@arm.com>,
	"Vincenzo Frascino" <vincenzo.frascino@arm.com>,
	"Marc Zyngier" <maz@kernel.org>,
	"Eugene Syromiatnikov" <esyr@redhat.com>,
	"Szabolcs Nagy" <szabolcs.nagy@arm.com>,
	"H . J . Lu " <hjl.tools@gmail.com>,
	"Andrew Jones" <drjones@redhat.com>,
	"Kees Cook" <keescook@chromium.org>,
	"Arnd Bergmann" <arnd@arndb.de>, "Jann Horn" <jannh@google.com>,
	"Richard Henderson" <richard.henderson@linaro.org>,
	"Kristina Martšenko" <kristina.martsenko@arm.com>,
	"Thomas Gleixner" <tglx@linutronix.de>,
	"Florian Weimer" <fweimer@redhat.com>,
	"Sudakshina Das" <sudi.das@arm.com>,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org,
	linux-fsdevel@vger.kernel.org
Subject: Re: [PATCH v8 00/11] arm64: Branch Target Identification support
Date: Fri, 13 Mar 2020 12:59:27 +0000	[thread overview]
Message-ID: <20200313125927.GE5528@sirena.org.uk> (raw)
In-Reply-To: <20200312184211.GA3849205@arrakis.emea.arm.com>

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On Thu, Mar 12, 2020 at 06:42:11PM +0000, Catalin Marinas wrote:
> On Wed, Mar 11, 2020 at 05:25:56PM +0000, Mark Brown wrote:
> > On Wed, Mar 11, 2020 at 04:28:58PM +0000, Catalin Marinas wrote:

> > > Can we not change aarch64_insn_is_nop() to actually return true only for
> > > NOP and ignore everything else in the hint space? We tend to re-use the

> > ignored. This isn't extensive userspace testing though.  Adding
> > whitelisting of the BTI and PAC hints would definitely be a safer as a
> > first step though.  I can post either version?

> I thought BTI and PAC are already whitelisted in mainline as they fall
> into the hint space (by whitelisting I mean you can probe them).

This was in the context of your comment above about modifying
aarch64_insn_is_nop() - if we do that and nothing else then we'd remove
the current whitelisting.

> I'm trying to understand how the BTI patches affect the current uprobes
> support and what is needed. Executing BTI or PCI?SP out of line should
> be fine as they don't generate a BTI exception (the BRK doesn't either,
> just the normal debug exception).

Right.

> I think (it needs checking) that BRK preserves the PSTATE.BTYPE in SPSR.

Yes, Exception_SoftwareBreakpoint preserves PSTATE.BTYPE.

> If we probe an instruction in a guarded page and then we single-step it
> in a non-guarded page, we'll miss a potential BTI fault. Is this an
> issue?

Obviously the main thing here is that if we miss faults then that's
potentially opening something that could be used as part of an exploit
chain.  I'm not aware of any sensible applications that would generate
the exceptions in normal operation.

> If we are to keep the BTI faulting behaviour, we'd need an additional
> xol page, guarded, and to find a way to report the original probed
> address of the fault rather than the xol page.

Yes, or just accept the inaccurate fault address which isn't good but
might be the least worst thing if there's issues with reporting the
original address.

> So, IIUC, we don't have an issue with the actual BTI or PACI?SP
> instructions but rather the other instructions that would not fault with
> the BTI support. While we should try to address this, I think the
> important bit now is not to break the existing uprobes support when
> running a binary with BTI enabled.

I think so, and as far as my ability to tell goes the worst consequence
would be missing exceptions like you say.  That's not great but it's at
least an extra hoop people have to jump through.

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