From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
To: robh+dt@kernel.org, andrew@lunn.ch, f.fainelli@gmail.com,
linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org
Cc: jianxin.pan@amlogic.com, davem@davemloft.net,
netdev@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Subject: [PATCH RFC v2 00/11] dwmac-meson8b Ethernet RX delay configuration
Date: Wed, 29 Apr 2020 22:16:33 +0200 [thread overview]
Message-ID: <20200429201644.1144546-1-martin.blumenstingl@googlemail.com> (raw)
The Ethernet TX performance has been historically bad on Meson8b and
Meson8m2 SoCs because high packet loss was seen. I found out that this
was related (yet again) to the RGMII TX delay configuration.
In the process of discussing the big picture (and not just a single
patch) [0] with Andrew I discovered that the IP block behind the
dwmac-meson8b driver actually seems to support the configuration of the
RGMII RX delay (at least on the Meson8b SoC generation).
Since I sent the last RFC I got additional documentation from Jianxin
(many thanks!). Also I have discovered some more interesting details:
- Meson8b Odroid-C1 requires an RX delay (by either the PHY or the MAC)
Based on the vendor u-boot code (not upstream) I assume that it will
be the same for all Meson8b and Meson8m2 boards
- Khadas VIM2 seems to have the RX delay built into the PCB trace
length. When I enable the RX delay on the PHY or MAC I can't get any
data through. I expect that we will have the same situation on all
GXBB, GXM, AXG, G12A, G12B and SM1 boards
Changes since RFC v1 at [1]:
- add support for the timing adjustment clock input (dt-bindings and
in the driver) thanks to the input from the unnamed Ethernet engineer
at Amlogic. This is the missing link between the fclk_div2 clock and
the Ethernet controller on Meson8b (no traffic would flow if that
clock was disabled)
- add support fot the amlogic,rx-delay-ns property. The only supported
values so far are 0ns and 2ns. The registers seem to allow more
precise timing adjustments, but I could not make that work so far.
- add more register documentation (for the new RX delay bits) and
unified the placement of existing register documentation. Again,
thanks to Jianxin and the unnamed Ethernet engineer at Amlogic
- DO NOT MERGE: .dts patches to show the conversion of the Meson8b
and Meson8m2 boards to "rgmii-id". I didn't have time for all arm64
patches yet, but these will switch to phy-mode = "rgmii-txid" with
amlogic,rx-delay-ns = <0> (because the delay seems to be provided by
the PCB trace length).
[0] https://patchwork.kernel.org/patch/11309891/
[1] https://patchwork.kernel.org/cover/11310719/
Martin Blumenstingl (11):
dt-bindings: net: meson-dwmac: Add the amlogic,rx-delay-ns property
dt-bindings: net: dwmac-meson: Document the "timing-adjustment" clock
net: stmmac: dwmac-meson8b: use FIELD_PREP instead of open-coding it
net: stmmac: dwmac-meson8b: Move the documentation for the TX delay
net: stmmac: dwmac-meson8b: Add the PRG_ETH0_ADJ_* bits
net: stmmac: dwmac-meson8b: Fetch the "timing-adjustment" clock
net: stmmac: dwmac-meson8b: Make the clock enabling code re-usable
net: stmmac: dwmac-meson8b: add support for the RX delay configuration
arm64: dts: amlogic: Add the Ethernet "timing-adjustment" clock
ARM: dts: meson: Add the Ethernet "timing-adjustment" clock
ARM: dts: meson: Switch existing boards with RGMII PHY to "rgmii-id"
.../bindings/net/amlogic,meson-dwmac.yaml | 23 ++-
arch/arm/boot/dts/meson8b-odroidc1.dts | 3 +-
arch/arm/boot/dts/meson8b.dtsi | 5 +-
arch/arm/boot/dts/meson8m2-mxiii-plus.dts | 4 +-
arch/arm/boot/dts/meson8m2.dtsi | 5 +-
arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 6 +-
.../boot/dts/amlogic/meson-g12-common.dtsi | 6 +-
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 5 +-
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 5 +-
.../ethernet/stmicro/stmmac/dwmac-meson8b.c | 140 ++++++++++++++----
10 files changed, 150 insertions(+), 52 deletions(-)
--
2.26.2
next reply other threads:[~2020-04-29 20:17 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-29 20:16 Martin Blumenstingl [this message]
2020-04-29 20:16 ` [PATCH RFC v2 01/11] dt-bindings: net: meson-dwmac: Add the amlogic,rx-delay-ns property Martin Blumenstingl
2020-05-01 15:26 ` Andrew Lunn
2020-05-12 14:51 ` Rob Herring
2020-04-29 20:16 ` [PATCH RFC v2 02/11] dt-bindings: net: dwmac-meson: Document the "timing-adjustment" clock Martin Blumenstingl
2020-05-01 15:27 ` Andrew Lunn
2020-05-01 21:09 ` Rob Herring
2020-05-01 21:53 ` Martin Blumenstingl
2020-05-10 22:34 ` Martin Blumenstingl
2020-04-29 20:16 ` [PATCH RFC v2 03/11] net: stmmac: dwmac-meson8b: use FIELD_PREP instead of open-coding it Martin Blumenstingl
2020-05-01 15:28 ` Andrew Lunn
2020-04-29 20:16 ` [PATCH RFC v2 04/11] net: stmmac: dwmac-meson8b: Move the documentation for the TX delay Martin Blumenstingl
2020-05-01 15:29 ` Andrew Lunn
2020-04-29 20:16 ` [PATCH RFC v2 05/11] net: stmmac: dwmac-meson8b: Add the PRG_ETH0_ADJ_* bits Martin Blumenstingl
2020-05-01 15:33 ` Andrew Lunn
2020-04-29 20:16 ` [PATCH RFC v2 06/11] net: stmmac: dwmac-meson8b: Fetch the "timing-adjustment" clock Martin Blumenstingl
2020-05-01 15:35 ` Andrew Lunn
2020-04-29 20:16 ` [PATCH RFC v2 07/11] net: stmmac: dwmac-meson8b: Make the clock enabling code re-usable Martin Blumenstingl
2020-05-01 15:37 ` Andrew Lunn
2020-04-29 20:16 ` [PATCH RFC v2 08/11] net: stmmac: dwmac-meson8b: add support for the RX delay configuration Martin Blumenstingl
2020-05-01 15:44 ` Andrew Lunn
2020-05-01 17:10 ` Martin Blumenstingl
2020-04-29 20:16 ` [PATCH DO NOT MERGE v2 09/11] arm64: dts: amlogic: Add the Ethernet "timing-adjustment" clock Martin Blumenstingl
2020-04-29 20:16 ` [PATCH DO NOT MERGE v2 10/11] ARM: dts: meson: " Martin Blumenstingl
2020-04-29 20:16 ` [PATCH DO NOT MERGE v2 11/11] ARM: dts: meson: Switch existing boards with RGMII PHY to "rgmii-id" Martin Blumenstingl
2020-04-29 21:29 ` [PATCH RFC v2 00/11] dwmac-meson8b Ethernet RX delay configuration Andrew Lunn
2020-05-01 14:49 ` Martin Blumenstingl
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