From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C9FCCC433E2 for ; Fri, 22 May 2020 12:26:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A74DA206B6 for ; Fri, 22 May 2020 12:26:07 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="W+W1vlh8" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729838AbgEVM0C (ORCPT ); Fri, 22 May 2020 08:26:02 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:46602 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728587AbgEVMZp (ORCPT ); Fri, 22 May 2020 08:25:45 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 04MCPcuW069723; Fri, 22 May 2020 07:25:38 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1590150338; bh=eXBSMpQf3dYh5WskBCPeXjZB//cH+6CVGFfywycbfVc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=W+W1vlh8rBwFzYozp+8gTg6pAqO+4B6sWPuMR/XOahmKRGfI1KGb7w05ML0ODtXfc Te+L5q0TC2g/4sLXy4QgOvWQX63JyAImM7JNddXjuHLslXPXOEBeE80d+cRSA90NAV i35gp3BKsU39aLmdgjKoAYNuaW6Fva00FyZ24UwE= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 04MCPbHU119223 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 22 May 2020 07:25:37 -0500 Received: from DFLE110.ent.ti.com (10.64.6.31) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Fri, 22 May 2020 07:25:37 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Fri, 22 May 2020 07:25:37 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 04MCPbSP008000; Fri, 22 May 2020 07:25:37 -0500 From: Dan Murphy To: , , , , CC: , , , Dan Murphy Subject: [PATCH net-next v2 4/4] net: dp83869: Add RGMII internal delay configuration Date: Fri, 22 May 2020 07:25:34 -0500 Message-ID: <20200522122534.3353-5-dmurphy@ti.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200522122534.3353-1-dmurphy@ti.com> References: <20200522122534.3353-1-dmurphy@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add RGMII internal delay configuration for Rx and Tx. Signed-off-by: Dan Murphy --- drivers/net/phy/dp83869.c | 101 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 101 insertions(+) diff --git a/drivers/net/phy/dp83869.c b/drivers/net/phy/dp83869.c index cfb22a21a2e6..a9008d32e2b6 100644 --- a/drivers/net/phy/dp83869.c +++ b/drivers/net/phy/dp83869.c @@ -99,6 +99,14 @@ #define DP83869_OP_MODE_MII BIT(5) #define DP83869_SGMII_RGMII_BRIDGE BIT(6) +/* RGMIIDCTL bits */ +#define DP83869_RGMII_TX_CLK_DELAY_SHIFT 4 +#define DP83869_RGMII_CLK_DELAY_INV 0 + +static int dp83869_internal_delay[] = {250, 500, 750, 1000, 1250, 1500, 1750, + 2000, 2250, 2500, 2750, 3000, 3250, + 3500, 3750, 4000}; + enum { DP83869_PORT_MIRRORING_KEEP, DP83869_PORT_MIRRORING_EN, @@ -108,6 +116,8 @@ enum { struct dp83869_private { int tx_fifo_depth; int rx_fifo_depth; + u32 rx_id_delay; + u32 tx_id_delay; int io_impedance; int port_mirroring; bool rxctrl_strap_quirk; @@ -182,6 +192,7 @@ static int dp83869_of_init(struct phy_device *phydev) struct dp83869_private *dp83869 = phydev->priv; struct device *dev = &phydev->mdio.dev; struct device_node *of_node = dev->of_node; + int delay_size = ARRAY_SIZE(dp83869_internal_delay); int ret; if (!of_node) @@ -232,6 +243,26 @@ static int dp83869_of_init(struct phy_device *phydev) &dp83869->tx_fifo_depth)) dp83869->tx_fifo_depth = DP83869_PHYCR_FIFO_DEPTH_4_B_NIB; + dp83869->rx_id_delay = DP83869_RGMII_CLK_DELAY_INV; + ret = of_property_read_u32(of_node, "rx-internal-delay-ps", + &dp83869->rx_id_delay); + if (!ret && dp83869->rx_id_delay > dp83869_internal_delay[delay_size]) { + phydev_err(phydev, + "rx-internal-delay value of %u out of range\n", + dp83869->rx_id_delay); + return -EINVAL; + } + + dp83869->tx_id_delay = DP83869_RGMII_CLK_DELAY_INV; + ret = of_property_read_u32(of_node, "tx-internal-delay-ps", + &dp83869->tx_id_delay); + if (!ret && dp83869->tx_id_delay > dp83869_internal_delay[delay_size]) { + phydev_err(phydev, + "tx-internal-delay value of %u out of range\n", + dp83869->tx_id_delay); + return -EINVAL; + } + return ret; } #else @@ -270,6 +301,29 @@ static int dp83869_configure_rgmii(struct phy_device *phydev, return ret; } +static int dp83869_verify_rgmii_cfg(struct phy_device *phydev) +{ + struct dp83869_private *dp83869 = phydev->priv; + + /* RX delay *must* be specified if internal delay of RX is used. */ + if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || + phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) && + dp83869->rx_id_delay == DP83869_RGMII_CLK_DELAY_INV) { + phydev_err(phydev, "ti,rx-internal-delay must be specified\n"); + return -EINVAL; + } + + /* TX delay *must* be specified if internal delay of TX is used. */ + if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || + phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) && + dp83869->tx_id_delay == DP83869_RGMII_CLK_DELAY_INV) { + phydev_err(phydev, "ti,tx-internal-delay must be specified\n"); + return -EINVAL; + } + + return 0; +} + static int dp83869_configure_mode(struct phy_device *phydev, struct dp83869_private *dp83869) { @@ -371,6 +425,12 @@ static int dp83869_config_init(struct phy_device *phydev) { struct dp83869_private *dp83869 = phydev->priv; int ret, val; + int delay_size = ARRAY_SIZE(dp83869_internal_delay); + int delay = 0; + + ret = dp83869_verify_rgmii_cfg(phydev); + if (ret) + return ret; ret = dp83869_configure_mode(phydev, dp83869); if (ret) @@ -394,6 +454,47 @@ static int dp83869_config_init(struct phy_device *phydev) dp83869->clk_output_sel << DP83869_IO_MUX_CFG_CLK_O_SEL_SHIFT); + if (phy_interface_is_rgmii(phydev)) { + val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIICTL); + + val &= ~(DP83869_RGMII_TX_CLK_DELAY_EN | DP83869_RGMII_RX_CLK_DELAY_EN); + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) + val |= (DP83869_RGMII_TX_CLK_DELAY_EN | DP83869_RGMII_RX_CLK_DELAY_EN); + + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) + val |= DP83869_RGMII_TX_CLK_DELAY_EN; + + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) + val |= DP83869_RGMII_RX_CLK_DELAY_EN; + + phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIICTL, val); + + if (dp83869->rx_id_delay) { + val = phy_get_delay_index(phydev, + &dp83869_internal_delay[0], + delay_size, + dp83869->rx_id_delay); + if (val < 0) + return val; + + delay |= val; + } + + if (dp83869->tx_id_delay) { + val = phy_get_delay_index(phydev, + &dp83869_internal_delay[0], + delay_size, + dp83869->tx_id_delay); + if (val < 0) + return val; + + delay |= val << DP83869_RGMII_TX_CLK_DELAY_SHIFT; + } + + phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIIDCTL, + delay); + } + return ret; } -- 2.26.2