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Thu, 08 Oct 2020 06:11:21 -0700 (PDT) Date: Thu, 8 Oct 2020 18:41:15 +0530 From: Manivannan Sadhasivam To: Gokul Sriram Palanisamy Cc: sboyd@kernel.org, agross@kernel.org, bjorn.andersson@linaro.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, sricharan@codeaurora.org Subject: Re: [PATCH v3 3/3] arm64: dts: Enabled MHI device over PCIe Message-ID: <20201008131115.GA23649@linux> References: <1602160344-19586-1-git-send-email-gokulsri@codeaurora.org> <1602160344-19586-4-git-send-email-gokulsri@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1602160344-19586-4-git-send-email-gokulsri@codeaurora.org> User-Agent: Mutt/1.9.4 (2018-02-28) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On Thu, Oct 08, 2020 at 06:02:24PM +0530, Gokul Sriram Palanisamy wrote: > Enabled MHI device support over PCIe and added memory > reservation required for MHI enabled QCN9000 PCIe card. > > Signed-off-by: Gokul Sriram Palanisamy > --- > arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi | 47 ++++++++++++++++++++++++++++++ > 1 file changed, 47 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi > index 0827055..e5c1ec0 100644 > --- a/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi > +++ b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi > @@ -24,6 +24,22 @@ > device_type = "memory"; > reg = <0x0 0x40000000 0x0 0x20000000>; > }; > + > + reserved-memory { > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + qcn9000_pcie0: memory@50f00000 { > + no-map; > + reg = <0x0 0x50f00000 0x0 0x03700000>; > + }; > + > + qcn9000_pcie1: memory@54600000 { > + no-map; > + reg = <0x0 0x54600000 0x0 0x03700000>; > + }; > + }; > }; > > &blsp1_spi1 { > @@ -45,11 +61,42 @@ > &pcie0 { > status = "ok"; > perst-gpio = <&tlmm 58 0x1>; > + > + pcie0_rp: pcie0_rp { > + reg = <0 0 0 0 0>; > + > + status = "ok"; > + mhi_0: qcom,mhi@0 { MHI doesn't support devicetree as of now so how is this supposed to work? Have you tested this series with mainline? Thanks, Mani > + reg = <0 0 0 0 0 >; > + > + qrtr_instance_id = <0x20>; > + base-addr = <0x50f00000>; > + m3-dump-addr = <0x53c00000>; > + etr-addr = <0x53d00000>; > + qcom,caldb-addr = <0x53e00000>; > + }; > + }; > }; > > &pcie1 { > status = "ok"; > perst-gpio = <&tlmm 61 0x1>; > + > + pcie1_rp: pcie1_rp { > + reg = <0 0 0 0 0>; > + > + status = "ok"; > + mhi_1: qcom,mhi@1 { > + reg = <0 0 0 0 0 >; > + > + qrtr_instance_id = <0x21>; > + base-addr = <0x54600000>; > + m3-dump-addr = <0x57300000>; > + etr-addr = <0x57400000>; > + qcom,caldb-addr = <0x57500000>; > + }; > + }; > + }; > }; > > &qmp_pcie_phy0 { > -- > 2.7.4 >