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Tue, 20 Oct 2020 22:10:36 -0700 (PDT) Date: Wed, 21 Oct 2020 13:10:31 +0800 From: Leo Yan To: =?iso-8859-1?Q?Andr=E9?= Przywara Cc: Arnaldo Carvalho de Melo , Peter Zijlstra , Ingo Molnar , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Wei Li , James Clark , Dave Martin , linux-kernel@vger.kernel.org, Al Grant Subject: Re: [PATCH v2 14/14] perf arm-spe: Add support for ARMv8.3-SPE Message-ID: <20201021051031.GE7226@leoy-ThinkPad-X240s> References: <20200929133917.9224-1-leo.yan@linaro.org> <20200929133917.9224-15-leo.yan@linaro.org> <9c74082b-fccf-7713-b98d-50da76c5d7af@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <9c74082b-fccf-7713-b98d-50da76c5d7af@arm.com> User-Agent: Mutt/1.9.4 (2018-02-28) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Oct 20, 2020 at 10:54:44PM +0100, André Przywara wrote: > On 29/09/2020 14:39, Leo Yan wrote: > > Hi, > > > From: Wei Li > > > > This patch is to support Armv8.3 extension for SPE, it adds alignment > > field in the Events packet and it supports the Scalable Vector Extension > > (SVE) for Operation packet and Events packet with two additions: > > > > - The vector length for SVE operations in the Operation Type packet; > > - The incomplete predicate and empty predicate fields in the Events > > packet. > > > > Signed-off-by: Wei Li > > Signed-off-by: Leo Yan > > --- > > .../arm-spe-decoder/arm-spe-pkt-decoder.c | 84 ++++++++++++++++++- > > .../arm-spe-decoder/arm-spe-pkt-decoder.h | 6 ++ > > 2 files changed, 87 insertions(+), 3 deletions(-) > > > > diff --git a/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c b/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c > > index 05a4c74399d7..3ec381fddfcb 100644 > > --- a/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c > > +++ b/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c > > @@ -342,14 +342,73 @@ int arm_spe_pkt_desc(const struct arm_spe_pkt *packet, char *buf, > > return ret; > > } > > } > > + if (idx > 2) { > > As I mentioned in the other patch, I doubt this extra comparison is > useful. Does that protect us from anything? It's the same reason with Event packet which have explained for replying patch 10, the condition is to respect the SPE specifiction: E[11], byte 1, bit [11], when SZ == 0b10 , or SZ == 0b11 Alignment. ... Otherwise this bit reads-as-zero. So we gives higher priority for checking payload size than the Event bit setting; if you have other thinking for this, please let me know. > > + if (payload & SPE_EVT_PKT_ALIGNMENT) { > > Mmh, but this is bit 11, right? Yes. > So would need to go into the (idx > 1) > section (covering bits 8-15)? Another reason to ditch this comparison above. As has explained in patch 10, idx is not the same thing with "sz" field; "idx" stands for payload length in bytes, so: idx = 1 << sz The spec defines the sz is 2 or 3, thus idx is 4 or 8; so this is why here use the condition "(idx > 2)". I think here need to refine code for more explict expression so can avoid confusion. So I think it's better to condition such like: if (payload_len >= 4) { ... } > > + ret = snprintf(buf, buf_len, " ALIGNMENT"); > > + if (ret < 0) > > + return ret; > > + buf += ret; > > + blen -= ret; > > Shouldn't we use the new arm_spe_pkt_snprintf() function here as well? > Or is there a reason that this doesn't work? Goot point. Will change to use arm_spe_pkt_snprintf(). > > + } > > + if (payload & SPE_EVT_PKT_SVE_PARTIAL_PREDICATE) { > > + ret = snprintf(buf, buf_len, " SVE-PARTIAL-PRED"); > > + if (ret < 0) > > + return ret; > > + buf += ret; > > + blen -= ret; > > + } > > + if (payload & SPE_EVT_PKT_SVE_EMPTY_PREDICATE) { > > + ret = snprintf(buf, buf_len, " SVE-EMPTY-PRED"); > > + if (ret < 0) > > + return ret; > > + buf += ret; > > + blen -= ret; > > + } > > + } > > + > > return buf_len - blen; > > > > case ARM_SPE_OP_TYPE: > > switch (idx) { > > case SPE_OP_PKT_HDR_CLASS_OTHER: > > - return arm_spe_pkt_snprintf(&buf, &blen, > > - payload & SPE_OP_PKT_OTHER_SUBCLASS_COND ? > > - "COND-SELECT" : "INSN-OTHER"); > > + if ((payload & SPE_OP_PKT_OTHER_SVE_SUBCLASS_MASK) == > > + SPE_OP_PKT_OTHER_SUBCLASS_SVG_OP) { > > + > > + ret = arm_spe_pkt_snprintf(&buf, &blen, "SVE-OTHER"); > > + if (ret < 0) > > + return ret; > > + > > + /* Effective vector length: step is 32 bits */ > > + ret = arm_spe_pkt_snprintf(&buf, &blen, " EVLEN %d", > > + 32 << ((payload & SPE_OP_PKT_SVE_EVL_MASK) >> > > + SPE_OP_PKT_SVE_EVL_SHIFT)); > > Can you move this into a macro, and add a comment about how this works? > People might get confused over the "32 << something". Yeah, will refine for it. Thanks, Leo