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Wed, 21 Oct 2020 03:17:53 -0700 (PDT) Date: Wed, 21 Oct 2020 18:17:48 +0800 From: Leo Yan To: =?iso-8859-1?Q?Andr=E9?= Przywara Cc: Arnaldo Carvalho de Melo , Peter Zijlstra , Ingo Molnar , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Wei Li , James Clark , Dave Martin , linux-kernel@vger.kernel.org, Al Grant Subject: Re: [PATCH v2 14/14] perf arm-spe: Add support for ARMv8.3-SPE Message-ID: <20201021101748.GB3194@leoy-ThinkPad-X240s> References: <20200929133917.9224-1-leo.yan@linaro.org> <20200929133917.9224-15-leo.yan@linaro.org> <9c74082b-fccf-7713-b98d-50da76c5d7af@arm.com> <20201021051031.GE7226@leoy-ThinkPad-X240s> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: User-Agent: Mutt/1.9.4 (2018-02-28) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Oct 21, 2020 at 10:26:07AM +0100, André Przywara wrote: > On 21/10/2020 06:10, Leo Yan wrote: > > Hi, > > > On Tue, Oct 20, 2020 at 10:54:44PM +0100, Andr� Przywara wrote: > >> On 29/09/2020 14:39, Leo Yan wrote: > >> > >> Hi, > >> > >>> From: Wei Li > >>> > >>> This patch is to support Armv8.3 extension for SPE, it adds alignment > >>> field in the Events packet and it supports the Scalable Vector Extension > >>> (SVE) for Operation packet and Events packet with two additions: > >>> > >>> - The vector length for SVE operations in the Operation Type packet; > >>> - The incomplete predicate and empty predicate fields in the Events > >>> packet. > >>> > >>> Signed-off-by: Wei Li > >>> Signed-off-by: Leo Yan > >>> --- > >>> .../arm-spe-decoder/arm-spe-pkt-decoder.c | 84 ++++++++++++++++++- > >>> .../arm-spe-decoder/arm-spe-pkt-decoder.h | 6 ++ > >>> 2 files changed, 87 insertions(+), 3 deletions(-) > >>> > >>> diff --git a/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c b/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c > >>> index 05a4c74399d7..3ec381fddfcb 100644 > >>> --- a/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c > >>> +++ b/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c > >>> @@ -342,14 +342,73 @@ int arm_spe_pkt_desc(const struct arm_spe_pkt *packet, char *buf, > >>> return ret; > >>> } > >>> } > >>> + if (idx > 2) { > >> > >> As I mentioned in the other patch, I doubt this extra comparison is > >> useful. Does that protect us from anything? > > > > It's the same reason with Event packet which have explained for replying > > patch 10, the condition is to respect the SPE specifiction: > > > > E[11], byte 1, bit [11], when SZ == 0b10 , or SZ == 0b11 > > Alignment. > > ... > > Otherwise this bit reads-as-zero. > > > > So we gives higher priority for checking payload size than the Event > > bit setting; if you have other thinking for this, please let me know. > > Ah, thanks for pointing this out. It looks like a bug in the manual > then, because I don't see why bit 11 should be any different from bits > [10:8] and bits [15:12] in this respect. And in the diagrams above you > clearly see bit 11 being shown even when SZ == 0b01. > > I will try to follow this up here. Thanks for following up! > >>> + if (payload & SPE_EVT_PKT_ALIGNMENT) { > >> > >> Mmh, but this is bit 11, right? > > > > Yes. > > > >> So would need to go into the (idx > 1) > >> section (covering bits 8-15)? Another reason to ditch this comparison above. > > > > As has explained in patch 10, idx is not the same thing with "sz" > > field; "idx" stands for payload length in bytes, so: > > > > idx = 1 << sz > > > > The spec defines the sz is 2 or 3, thus idx is 4 or 8; so this is why > > here use the condition "(idx > 2)". > > > > I think here need to refine code for more explict expression so can > > avoid confusion. So I think it's better to condition such like: > > > > if (payload_len >= 4) { > > Yes, that would be (or have been) more helpful, but as mentioned in the > other patch, I'd rather see those comparisons go entirely. Agree. Will remove comparisons in next version. Thanks, Leo