linux-kernel.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
From: Andrew Lunn <andrew@lunn.ch>
To: Pavana Sharma <pavana.sharma@digi.com>
Cc: f.fainelli@gmail.com, davem@davemloft.net,
	gregkh@linuxfoundation.org, kuba@kernel.org,
	linux-kernel@vger.kernel.org, netdev@vger.kernel.org,
	vivien.didelot@gmail.com
Subject: Re: [PATCH v5 3/3] net: dsa: mv88e6xxx: Add support for mv88e6393x family of Marvell
Date: Wed, 28 Oct 2020 13:21:15 +0100	[thread overview]
Message-ID: <20201028122115.GC933237@lunn.ch> (raw)
In-Reply-To: <e5fdcddeda21884a21162e441d1e8a04994f2825.1603837679.git.pavana.sharma@digi.com>

On Wed, Oct 28, 2020 at 10:09:50AM +1000, Pavana Sharma wrote:
> The Marvell 88E6393X device is a single-chip integration of a 11-port
> Ethernet switch with eight integrated Gigabit Ethernet (GbE) transceivers
> and three 10-Gigabit interfaces.
> 
> This patch adds functionalities specific to mv88e6393x family (88E6393X,
> 88E6193X and 88E6191X)

Please break this patch up a bit into preparation patches, and the
last patch actually adding support for the new family.

e.g. serdes_get_lane() returning -ENODEV should be a patch of its
own. That should hopefully answer the question which

ommit 5122d4ec9e8053a5944bf77db6bd6c89143531d7
Author: Vivien Didelot <vivien.didelot@gmail.com>
Date:   Sat Aug 31 16:18:30 2019 -0400

    net: dsa: mv88e6xxx: simplify .serdes_get_lane
    
    Because the mapping between a SERDES interface and its lane is static,
    we don't need to stick with negative error codes actually and we can
    simply return 0 if there is no lane, just like the IRQ mapping.
    
    This way we can keep a simple and intuitive API using unsigned lane
    numbers while simplifying the implementations with single return
    statements

raises.

> +static const struct mv88e6xxx_ops mv88e6193x_ops = {
> +	/* MV88E6XXX_FAMILY_6393 */
> +	.setup_errata = mv88e6393x_setup_errata,
> +	.irl_init_all = mv88e6390_g2_irl_init_all,
> +	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
> +	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
> +	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
> +	.phy_read = mv88e6xxx_g2_smi_phy_read,
> +	.phy_write = mv88e6xxx_g2_smi_phy_write,
> +	.port_set_link = mv88e6xxx_port_set_link,
> +	.port_set_speed_duplex = mv88e6393x_port_set_speed_duplex,
> +	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
> +	.port_tag_remap = mv88e6390_port_tag_remap,
> +	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
> +	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
> +	.port_set_ether_type = mv88e6393x_port_set_ether_type,
> +	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
> +	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
> +	.port_pause_limit = mv88e6390_port_pause_limit,
> +	.port_set_cmode = mv88e6393x_port_set_cmode,
> +	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
> +	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
> +	.port_get_cmode = mv88e6352_port_get_cmode,
> +	.stats_snapshot = mv88e6390_g1_stats_snapshot,
> +	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
> +	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
> +	.stats_get_strings = mv88e6320_stats_get_strings,
> +	.stats_get_stats = mv88e6390_stats_get_stats,
> +	.set_cpu_port = mv88e6393x_port_set_cpu_dest,
> +	.set_egress_port = mv88e6393x_set_egress_port,
> +	.watchdog_ops = &mv88e6390_watchdog_ops,
> +	.mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu,
> +	.pot_clear = mv88e6xxx_g2_pot_clear,
> +	.reset = mv88e6352_g1_reset,
> +	.rmu_disable = mv88e6390_g1_rmu_disable,
> +	.vtu_getnext = mv88e6390_g1_vtu_getnext,
> +	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
> +	.serdes_power = mv88e6393x_serdes_power,
> +	.serdes_get_lane = mv88e6393x_serdes_get_lane,
> +	/* Check status register pause & lpa register */
> +	.serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
> +	.serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
> +	.serdes_irq_enable = mv88e6393x_serdes_irq_enable,
> +	.serdes_irq_status = mv88e6393x_serdes_irq_status,
> +	.gpio_ops = &mv88e6352_gpio_ops,
> +	.avb_ops = &mv88e6390_avb_ops,
> +	.ptp_ops = &mv88e6352_ptp_ops,
> +	.phylink_validate = mv88e6393x_phylink_validate,
> +};

> diff --git a/drivers/net/dsa/mv88e6xxx/chip.h b/drivers/net/dsa/mv88e6xxx/chip.h
> index 823ae89e5fca..03c0466ab4ae 100644
> --- a/drivers/net/dsa/mv88e6xxx/chip.h
> +++ b/drivers/net/dsa/mv88e6xxx/chip.h
> @@ -63,6 +63,8 @@ enum mv88e6xxx_model {
>  	MV88E6190,
>  	MV88E6190X,
>  	MV88E6191,
> +	MV88E6191X,

Is the 6191X part of the 6193 family? Not the 6390, like the 6191 is?
Or do we have the 6191 in the wrong family?

> +	MV88E6193X,

You don't add any _ops structure for the 6193x. How is it different?
Can you make your best guess at the ops structure. Also, what about
the 6191X?

>  	MV88E6220,
>  	MV88E6240,
>  	MV88E6250,
> @@ -75,6 +77,7 @@ enum mv88e6xxx_model {
>  	MV88E6352,
>  	MV88E6390,
>  	MV88E6390X,
> +	MV88E6393X,
>  };
>  
>  enum mv88e6xxx_family {
> @@ -90,6 +93,7 @@ enum mv88e6xxx_family {
>  	MV88E6XXX_FAMILY_6351,	/* 6171 6175 6350 6351 */
>  	MV88E6XXX_FAMILY_6352,	/* 6172 6176 6240 6352 */
>  	MV88E6XXX_FAMILY_6390,  /* 6190 6190X 6191 6290 6390 6390X */
> +	MV88E6XXX_FAMILY_6393,	/* 6191X 6193X 6393X */
>  };

   Andrew

  parent reply	other threads:[~2020-10-28 23:14 UTC|newest]

Thread overview: 89+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <djc@djc.id.au; danc86@gmail.com[PATCH v2] Add support for mv88e6393x family of Marvell.>
2020-10-16  2:09 ` [PATCH v3] Add support for mv88e6393x family of Marvell Pavana Sharma
2020-10-16  2:37   ` Florian Fainelli
2020-10-17 19:30   ` Andrew Lunn
2020-10-26  5:52     ` [PATCH v4 0/3] " Pavana Sharma
2020-10-26  5:54       ` [PATCH v4 1/3] " Pavana Sharma
2020-10-26  8:58         ` kernel test robot
2020-10-27 19:10         ` kernel test robot
2020-10-26  5:58       ` [PATCH v4 2/3] Add phy interface for 5GBASER mode Pavana Sharma
2020-10-26 13:38         ` Andrew Lunn
2020-10-26 13:42         ` Florian Fainelli
2020-10-26  5:58       ` [PATCH v4 3/3] Change serdes lane parameter from u8 type to int Pavana Sharma
2020-10-26 13:43       ` [PATCH v4 0/3] Add support for mv88e6393x family of Marvell Florian Fainelli
2020-10-28  0:07         ` [PATCH v5 " Pavana Sharma
2020-10-28  0:08           ` [PATCH v5 1/3] net: phy: Add 5GBASER interface mode Pavana Sharma
2020-10-28 12:03             ` Andrew Lunn
2020-10-28  0:09           ` [PATCH v5 2/3] dt-bindings: net: Add 5GBASER phy " Pavana Sharma
2020-10-28 12:03             ` Andrew Lunn
2020-10-28  0:09           ` [PATCH v5 3/3] net: dsa: mv88e6xxx: Add support for mv88e6393x family of Marvell Pavana Sharma
2020-10-28  2:03             ` Marek Behun
2020-10-28 12:21             ` Andrew Lunn [this message]
2020-10-29  5:40               ` [PATCH v6 0/4] " Pavana Sharma
2020-10-29  5:41                 ` [PATCH v6 1/4] dt-bindings: net: Add 5GBASER phy interface mode Pavana Sharma
2020-10-29  5:42                 ` [PATCH v6 2/4] net: phy: Add 5GBASER " Pavana Sharma
2020-10-29  6:11                   ` Marek Behun
2020-10-29 12:42                   ` Andrew Lunn
2020-10-29  5:42                 ` [PATCH v6 3/4] net: dsa: mv88e6xxx: Add support for mv88e6393x family of Marvell Pavana Sharma
2020-10-29  6:31                   ` Marek Behun
2020-11-02  6:40                     ` [PATCH v7 0/4] " Pavana Sharma
2020-11-02  6:41                       ` [PATCH v7 1/4] dt-bindings: net: Add 5GBASER phy interface mode Pavana Sharma
2020-11-02  6:42                       ` [PATCH v7 2/4] net: phy: Add 5GBASER " Pavana Sharma
2020-11-02 13:09                         ` Andrew Lunn
2020-11-03  1:34                           ` Pavana Sharma
2020-11-03  2:12                             ` Florian Fainelli
2020-11-03  3:16                               ` Andrew Lunn
2020-11-03  8:48                                 ` [PATCH v8 0/4] Add support for mv88e6393x family of Marvell Pavana Sharma
2020-11-03  8:49                                   ` [PATCH v8 1/4] dt-bindings: net: Add 5GBASER phy interface mode Pavana Sharma
2020-11-06  1:42                                     ` Jakub Kicinski
2020-11-03  8:49                                   ` [PATCH v8 2/4] net: phy: Add 5GBASER " Pavana Sharma
2020-11-03  8:50                                   ` [PATCH v8 3/4] net: dsa: mv88e6xxx: Change serdes lane parameter from u8 type to int Pavana Sharma
2020-11-06  1:40                                     ` Jakub Kicinski
2020-11-03  8:50                                   ` [PATCH v8 4/4] net: dsa: mv88e6xxx: Add support for mv88e6393x family of Marvell Pavana Sharma
2020-11-06  1:52                                     ` Jakub Kicinski
2020-11-19  8:01                                       ` [PATCH v9 0/4] " Pavana Sharma
2020-11-19  8:02                                         ` [PATCH v9 1/4] dt-bindings: net: Add 5GBASER phy interface mode Pavana Sharma
2020-11-19  8:03                                         ` [PATCH v9 2/4] net: phy: Add 5GBASER " Pavana Sharma
2020-11-19  8:03                                         ` [PATCH v9 3/4] net: dsa: mv88e6xxx: Change serdes lane parameter from u8 type to int Pavana Sharma
2020-11-19  8:04                                         ` [PATCH v9 4/4] net: dsa: mv88e6xxx: Add support for mv88e6393x family of Marvell Pavana Sharma
2020-11-19 15:33                                           ` kernel test robot
2020-11-19 19:12                                           ` kernel test robot
2020-11-20  0:24                                             ` [PATCH v10 0/4] " Pavana Sharma
2020-11-20  0:25                                               ` [PATCH v10 1/4] dt-bindings: net: Add 5GBASER phy interface mode Pavana Sharma
2020-11-20  0:52                                                 ` Andrew Lunn
2020-11-20  0:25                                               ` [PATCH v10 2/4] net: phy: Add 5GBASER " Pavana Sharma
2020-11-20  0:55                                                 ` Andrew Lunn
2020-11-20  0:26                                               ` [PATCH v10 3/4] net: dsa: mv88e6xxx: Change serdes lane parameter from u8 type to int Pavana Sharma
2020-11-20  0:59                                                 ` Andrew Lunn
2020-11-20  0:26                                               ` [PATCH v10 4/4] net: dsa: mv88e6xxx: Add support for mv88e6393x family of Marvell Pavana Sharma
2020-11-20  1:29                                                 ` Andrew Lunn
2020-11-20  1:43                                                   ` Marek Behun
2020-11-20  1:54                                                     ` Andrew Lunn
2020-12-09  5:02                                                       ` [PATCH v11 0/4] " Pavana Sharma
2020-12-09  5:03                                                         ` [PATCH v11 1/4] dt-bindings: net: Add 5GBASER phy interface mode Pavana Sharma
2020-12-09 23:15                                                           ` Andrew Lunn
2020-12-10 13:43                                                             ` Pavana Sharma
2020-12-09  5:04                                                         ` [PATCH v11 2/4] net: phy: Add 5GBASER " Pavana Sharma
2020-12-09 23:18                                                           ` Andrew Lunn
2020-12-09  5:05                                                         ` [PATCH v11 3/4] net: dsa: mv88e6xxx: Change serdes lane parameter type from u8 type to int Pavana Sharma
2020-12-09 23:24                                                           ` Andrew Lunn
2020-12-09  5:05                                                         ` [PATCH v11 4/4] net: dsa: mv88e6xxx: Add support for mv88e6393x family of Marvell Pavana Sharma
2020-12-09 23:40                                                           ` Andrew Lunn
2020-12-09 19:37                                                         ` [PATCH v11 0/4] " Jakub Kicinski
2020-12-11 12:44                                                           ` [net-next PATCH v12 " Pavana Sharma
2020-12-11 12:46                                                             ` [net-next PATCH v12 1/4] dt-bindings: net: Add 5GBASER phy interface mode Pavana Sharma
2020-12-14 22:56                                                               ` Rob Herring
2020-12-11 12:46                                                             ` [net-next PATCH v12 2/4] net: phy: Add 5GBASER " Pavana Sharma
2020-12-11 12:49                                                             ` [net-next PATCH v12 3/4] net: dsa: mv88e6xxx: Change serdes lane parameter type from u8 type to int Pavana Sharma
2020-12-11 12:51                                                             ` [net-next PATCH v12 4/4] net: dsa: mv88e6xxx: Add support for mv88e6393x family of Marvell Pavana Sharma
2021-01-05 12:15                                                               ` Marek Behún
2021-01-06  0:45                                                                 ` Pavana Sharma
2021-01-06 12:20                                                                   ` Marek Behún
2020-11-02  6:43                       ` [PATCH v7 3/4] net: dsa: mv88e6xxx: Change serdes lane parameter from u8 type to int Pavana Sharma
2020-11-02 13:34                         ` Andrew Lunn
2020-11-02 13:40                         ` Andrew Lunn
2020-11-02  6:43                       ` [PATCH v7 4/4] net: dsa: mv88e6xxx: Add support for mv88e6393x family of Marvell Pavana Sharma
2020-11-02 13:12                       ` [PATCH v7 0/4] " Andrew Lunn
2020-10-29  5:43                 ` [PATCH v6 4/4] net: dsa: mv88e6xxx: Change serdes lane parameter from u8 to int Pavana Sharma
2020-10-29  6:07                 ` [PATCH v6 0/4] Add support for mv88e6393x family of Marvell Marek Behun
2020-10-28 23:12             ` [PATCH v5 3/3] net: dsa: mv88e6xxx: " Jakub Kicinski
2020-10-29  4:25             ` kernel test robot

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20201028122115.GC933237@lunn.ch \
    --to=andrew@lunn.ch \
    --cc=davem@davemloft.net \
    --cc=f.fainelli@gmail.com \
    --cc=gregkh@linuxfoundation.org \
    --cc=kuba@kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=netdev@vger.kernel.org \
    --cc=pavana.sharma@digi.com \
    --cc=vivien.didelot@gmail.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).